LIU Zhiwei 0968caa249 target/riscv: add vector extension field in CPURISCVState ... The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Backports ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 from qemu		2021-02-26 02:17:49 -05:00
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arm	target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64	2021-02-25 23:50:18 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: add vector extension field in CPURISCVState	2021-02-26 02:17:49 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00