LIU Zhiwei 0968caa249 target/riscv: add vector extension field in CPURISCVState ... The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Backports ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 from qemu		2021-02-26 02:17:49 -05:00
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insn_trans	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: Add the lowRISC Ibex CPU	2020-06-14 22:28:55 -04:00
cpu.h	target/riscv: add vector extension field in CPURISCVState	2021-02-26 02:17:49 -05:00
cpu_bits.h	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-03-22 02:18:02 -04:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2021-02-25 11:55:53 -05:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	target/riscv: Fix the range of pmpcfg of CSR funcion table	2021-02-25 23:35:21 -05:00
fpu_helper.c	target/riscv: rationalise softfloat includes	2019-11-18 21:17:03 -05:00
helper.h	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: Move the hfence instructions to the rvh decode	2021-02-25 11:59:49 -05:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
op_helper.c	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
pmp.c	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-08-08 16:55:52 -04:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-08-08 16:52:57 -04:00
translate.c	target/riscv: add vector extension field in CPURISCVState	2021-02-26 02:17:49 -05:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00