Charles Ferguson 0d0d054382 Add implementation of access to the ARM SPSR register. (#1178) ... The SPSR register is named within the Unicorn headers, but the code to access it is absent. This means that it will always read as 0 and ignore writes. This makes it harder to work with changes in processor mode, as the usual way to return from a CPU exception is a `MOVS pc, lr` for undefined instructions or `SUBS pc, lr, #4` for most other aborts - which implicitly restores the CPSR from SPSR. This change adds the access to the SPSR so that it can be read and written as the caller might expect. Backports commit 99097cab4c39fb3fc50eea8f0006954f62a149b2 from unicorn.		2020-01-14 09:57:55 -05:00
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arm	Add implementation of access to the ARM SPSR register. (#1178)	2020-01-14 09:57:55 -05:00
i386	check arguments, return error instead of raising exceptions. (#1125)	2020-01-14 09:00:11 -05:00
m68k	target/m68k: only change valid bits in CACR	2020-01-14 08:17:14 -05:00
mips	target/mips: Hard code size with MO_{8|16|32|64}	2020-01-07 18:30:39 -05:00
riscv	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00