Alistair Francis e1f49dc888 target/riscv: Implement checks for hfence ... Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Backports commit 2761db5fc20943bbd606b6fd49640ac000398de6 from qemu		2021-02-25 12:03:57 -05:00
..
insn_trans	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
cpu-param.h
cpu.c	target/riscv: Add the lowRISC Ibex CPU	2020-06-14 22:28:55 -04:00
cpu.h	riscv: Add helper to make NaN-boxing for FP register	2021-02-25 11:53:27 -05:00
cpu_bits.h	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-03-22 02:18:02 -04:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2021-02-25 11:55:53 -05:00
cpu_user.h
csr.c	target/riscv: Drop support for ISA spec version 1.09.1	2020-06-14 22:23:26 -04:00
fpu_helper.c
helper.h	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode	target/riscv: Move the hfence instructions to the rvh decode	2021-02-25 11:59:49 -05:00
instmap.h
Makefile.objs
op_helper.c	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
pmp.c
pmp.h
translate.c	target/riscv: Move the hfence instructions to the rvh decode	2021-02-25 11:59:49 -05:00
unicorn.c
unicorn.h