Aaron Lindsay e532ce610e target/arm: Don't do raw writes for PMINTENCLR ... Raw writes to this register when in KVM mode can cause interrupts to be raised (even when the PMU is disabled). Because the underlying state is already aliased to PMINTENSET (which already provides raw write functions), we can safely disable raw accesses to PMINTENCLR entirely. Backports commit 887c0f1544991f567543b7c214aa11ab0cea0a29 from qemu		2021-02-25 23:27:47 -05:00
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arm	target/arm: Don't do raw writes for PMINTENCLR	2021-02-25 23:27:47 -05:00
i386	target/i386: implement undocumented 'smsw r32' behavior	2021-02-25 23:23:51 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00