mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-26 00:45:32 +00:00
0d0d054382
The SPSR register is named within the Unicorn headers, but the code to access it is absent. This means that it will always read as 0 and ignore writes. This makes it harder to work with changes in processor mode, as the usual way to return from a CPU exception is a `MOVS pc, lr` for undefined instructions or `SUBS pc, lr, #4` for most other aborts - which implicitly restores the CPSR from SPSR. This change adds the access to the SPSR so that it can be read and written as the caller might expect. Backports commit 99097cab4c39fb3fc50eea8f0006954f62a149b2 from unicorn.
251 lines
8.1 KiB
C
251 lines
8.1 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/arm/arm.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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const int ARM_REGS_STORAGE_SIZE = offsetof(CPUARMState, tlb_table);
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static void arm_set_pc(struct uc_struct *uc, uint64_t address)
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{
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CPUArchState *state = uc->cpu->env_ptr;
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state->pc = address;
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state->regs[15] = address;
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}
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void arm_release(void* ctx);
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void arm_release(void* ctx)
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{
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TCGContext *s = (TCGContext *) ctx;
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struct uc_struct* uc = s->uc;
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ARMCPU* cpu = ARM_CPU(uc, uc->cpu);
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CPUArchState *env = &cpu->env;
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g_free(s->tb_ctx.tbs);
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g_free(cpu->cpreg_indexes);
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g_free(cpu->cpreg_values);
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g_free(cpu->cpreg_vmstate_indexes);
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g_free(cpu->cpreg_vmstate_values);
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g_free(env->pmsav7.drbar);
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g_free(env->pmsav7.drsr);
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g_free(env->pmsav7.dracr);
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release_common(ctx);
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}
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void arm_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->regs, 0, sizeof(env->regs));
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env->pc = 0;
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}
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int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) {
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*(uint32_t *)value = state->regs[regid - UC_ARM_REG_R0];
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} else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) {
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const float64 *d_reg = aa32_vfp_dreg(state, regid - UC_ARM_REG_D0);
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*(float64 *)value = *d_reg;
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} else {
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switch(regid) {
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case UC_ARM_REG_APSR:
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*(uint32_t *)value = cpsr_read(state) & CPSR_NZCV;
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break;
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case UC_ARM_REG_CPSR: {
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// Bits 20-23 should always read as zero.
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const uint32_t mask = 0xFF0FFFFF;
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*(uint32_t *)value = cpsr_read(state) & mask;
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break;
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}
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case UC_ARM_REG_SPSR:
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*(int32_t *)value = state->spsr;
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break;
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//case UC_ARM_REG_SP:
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case UC_ARM_REG_R13:
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*(uint32_t *)value = state->regs[13];
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break;
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//case UC_ARM_REG_LR:
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case UC_ARM_REG_R14:
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*(uint32_t *)value = state->regs[14];
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break;
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//case UC_ARM_REG_PC:
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case UC_ARM_REG_R15:
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*(uint32_t *)value = state->regs[15];
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break;
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case UC_ARM_REG_C1_C0_2:
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*(uint32_t *)value = state->cp15.cpacr_el1;
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break;
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case UC_ARM_REG_C13_C0_3:
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*(uint32_t *)value = state->cp15.tpidrro_el[0];
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break;
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case UC_ARM_REG_FPEXC:
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*(uint32_t *)value = state->vfp.xregs[ARM_VFP_FPEXC];
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break;
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case UC_ARM_REG_FPSCR:
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*(uint32_t *)value = vfp_get_fpscr(state);
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break;
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case UC_ARM_REG_IPSR:
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*(uint32_t *)value = xpsr_read(state) & XPSR_EXCP;
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break;
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case UC_ARM_REG_MSP:
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*(uint32_t *)value = helper_v7m_mrs(state, 8);
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break;
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case UC_ARM_REG_PSP:
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*(uint32_t *)value = helper_v7m_mrs(state, 9);
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break;
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case UC_ARM_REG_CONTROL:
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*(uint32_t *)value = helper_v7m_mrs(state, 20);
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break;
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}
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}
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}
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return 0;
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}
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int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) {
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state->regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
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} else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) {
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float64 *d_reg = aa32_vfp_dreg(state, regid - UC_ARM_REG_D0);
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*d_reg = *(float64 *)value;
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} else {
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switch(regid) {
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case UC_ARM_REG_APSR:
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cpsr_write(state, *(uint32_t *)value, CPSR_NZCV, CPSRWriteRaw);
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break;
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case UC_ARM_REG_CPSR: {
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// Bits 20-23 are considered reserved and should always read as zero.
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const uint32_t mask = 0xFF0FFFFF;
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cpsr_write(state, *(uint32_t *)value, mask, CPSRWriteRaw);
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break;
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}
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case UC_ARM_REG_SPSR:
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state->spsr = *(uint32_t *)value;
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break;
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//case UC_ARM_REG_SP:
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case UC_ARM_REG_R13:
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state->regs[13] = *(uint32_t *)value;
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break;
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//case UC_ARM_REG_LR:
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case UC_ARM_REG_R14:
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state->regs[14] = *(uint32_t *)value;
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break;
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//case UC_ARM_REG_PC:
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case UC_ARM_REG_R15:
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state->pc = (*(uint32_t *)value & ~1);
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state->thumb = (*(uint32_t *)value & 1);
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state->uc->thumb = (*(uint32_t *)value & 1);
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state->regs[15] = (*(uint32_t *)value & ~1);
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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break;
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case UC_ARM_REG_C1_C0_2:
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state->cp15.cpacr_el1 = *(uint32_t *)value;
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break;
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case UC_ARM_REG_C13_C0_3:
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state->cp15.tpidrro_el[0] = *(uint32_t *)value;
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break;
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case UC_ARM_REG_FPEXC:
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state->vfp.xregs[ARM_VFP_FPEXC] = *(uint32_t *)value;
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break;
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case UC_ARM_REG_FPSCR:
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vfp_set_fpscr(state, *(uint32_t *)value);
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break;
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case UC_ARM_REG_IPSR:
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xpsr_write(state, *(uint32_t *)value, XPSR_EXCP);
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break;
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case UC_ARM_REG_MSP:
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helper_v7m_msr(state, 8, *(uint32_t *)value);
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break;
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case UC_ARM_REG_PSP:
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helper_v7m_msr(state, 9, *(uint32_t *)value);
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break;
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case UC_ARM_REG_CONTROL:
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helper_v7m_msr(state, 20, *(uint32_t *)value);
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break;
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}
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}
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}
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return 0;
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}
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static bool arm_stop_interrupt(int intno)
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{
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switch(intno) {
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default:
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return false;
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case EXCP_UDEF:
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case EXCP_YIELD:
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return true;
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}
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}
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static uc_err arm_query(struct uc_struct *uc, uc_query_type type, size_t *result)
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{
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CPUState *mycpu = uc->cpu;
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CPUARMState *state = &ARM_CPU(uc, mycpu)->env;
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uint32_t mode;
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switch(type) {
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case UC_QUERY_MODE:
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// zero out ARM/THUMB mode
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mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);
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// THUMB mode or ARM MOde
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mode += ((state->thumb != 0) ? UC_MODE_THUMB : UC_MODE_ARM);
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*result = mode;
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return UC_ERR_OK;
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default:
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return UC_ERR_ARG;
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}
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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void armeb_uc_init(struct uc_struct* uc)
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#else
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void arm_uc_init(struct uc_struct* uc)
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#endif
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{
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register_accel_types(uc);
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arm_cpu_register_types(uc);
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tosa_machine_init_register_types(uc);
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uc->reg_read = arm_reg_read;
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uc->reg_write = arm_reg_write;
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uc->reg_reset = arm_reg_reset;
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uc->set_pc = arm_set_pc;
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uc->stop_interrupt = arm_stop_interrupt;
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uc->release = arm_release;
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uc->query = arm_query;
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uc_common_init(uc);
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}
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