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Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, X86)
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Python 3.9%
Java 1.5%
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Anup Patel 15e558e9cc riscv: Fix Stage2 SV32 page table walk 
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
is required to handle the 34bit intermediate physical address coming
from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2
SV32 level-0 page table will be 16KB in size with total 4096 enteries
where each entry maps 4MB of memory (same as Stage1 SV32 page table).

The get_physical_address() function is broken for Stage2 SV32 level-0
page table because it incorrectly computes output physical address for
Stage2 SV32 level-0 page table entry.

The root cause of the issue is that get_physical_address() uses the
"widened" variable to compute level-0 physical address mapping which
changes level-0 mapping size (instead of 4MB). We should use the
"widened" variable only for computing index of Stage2 SV32 level-0
page table.

Backports commit ee79e7cd47ef47074d7c20c221321c5d31d3683d from qemu
2020-04-30 20:54:08 -04:00
bindings python: handle UC_ERR_TIMEOUT, so sample_x86.py behaves like sample_x86.c 2020-01-14 09:53:10 -05:00
docs docs: we no longer requires python2 in building 2020-01-14 09:07:44 -05:00
include Timeout error () 2020-01-14 09:42:57 -05:00
msvc msvc: Define CONFIG_TCG 2019-01-30 13:52:30 -05:00
qemu riscv: Fix Stage2 SV32 page table walk 2020-04-30 20:54:08 -04:00
samples Timeout error () 2020-01-14 09:42:57 -05:00
tests Tests, fixes on third platform. () 2020-01-14 09:45:55 -05:00
.appveyor.yml MSYS test () 2017-06-25 10:11:35 +08:00
.gitignore target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
.travis.yml use new travis osx image and brew () 2018-01-05 10:29:49 +08:00
AUTHORS.TXT import 2015-08-21 15:04:50 +08:00
Brewfile Update Brewfile 2017-09-30 17:36:44 +07:00
ChangeLog update ChangeLog 2017-04-20 13:28:02 +08:00
config.mk Fix document file extension 2016-08-08 17:33:49 +09:00
COPYING import 2015-08-21 15:04:50 +08:00
COPYING.LGPL2 LGPL2 for all header files under include/unicorn/ 2017-12-16 10:08:42 +08:00
COPYING_GLIB glib_compat: add COPYING_GLIB 2016-12-27 10:15:08 +08:00
CREDITS.TXT Adding Philippe Antoine to CREDITS 2018-10-06 04:50:10 -04:00
install-cmocka-linux.sh Start moving examples in S files () 2017-06-25 10:14:22 +08:00
list.c callback to count number of instructions in uc_emu_start() should be executed first. fix 2017-06-16 13:22:38 +08:00
make.sh remove broken iOS builds () 2019-08-08 20:09:05 -04:00
Makefile uc: Restore armeb target 2019-04-19 15:29:25 -04:00
msvc.bat add msvc.bat 2017-04-21 15:35:40 +08:00
pkgconfig.mk bump extra version to 2 2017-04-21 15:30:40 +08:00
README.md add Clojure 2017-12-23 00:32:33 +08:00
uc.c Timeout error () 2020-01-14 09:42:57 -05:00
windows_export.bat Make the call out to visual studio extremely resilient 2017-01-02 03:32:48 -08:00

README.md

Unicorn Engine

Join the chat at https://gitter.im/unicorn-engine/chat

Build Status Build status

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

  • Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
  • Clean/simple/lightweight/intuitive architecture-neutral API
  • Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
  • Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
  • High performance via Just-In-Time compilation
  • Support for fine-grained instrumentation at various levels
  • Thread-safety by design
  • Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contact us via mailing list, email or twitter for any questions.

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.