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Anup Patel 15e558e9cc riscv: Fix Stage2 SV32 page table walk 
As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
is required to handle the 34bit intermediate physical address coming
from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2
SV32 level-0 page table will be 16KB in size with total 4096 enteries
where each entry maps 4MB of memory (same as Stage1 SV32 page table).

The get_physical_address() function is broken for Stage2 SV32 level-0
page table because it incorrectly computes output physical address for
Stage2 SV32 level-0 page table entry.

The root cause of the issue is that get_physical_address() uses the
"widened" variable to compute level-0 physical address mapping which
changes level-0 mapping size (instead of 4MB). We should use the
"widened" variable only for computing index of Stage2 SV32 level-0
page table.

Backports commit ee79e7cd47ef47074d7c20c221321c5d31d3683d from qemu
2020-04-30 20:54:08 -04:00
..
accel tcg: Remove softmmu code_gen_buffer fixed address 2020-04-30 07:03:06 -04:00
crypto crypto: Clean up includes 2018-02-19 00:47:40 -05:00
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs docs/devel/memory.txt: Document _with_attrs accessors 2018-10-04 04:46:26 -04:00
fpu softfloat: Fix BAD_SHIFT from normalizeFloatx80Subnormal 2020-04-30 07:22:57 -04:00
hw Expose different 32-bit ARM CPU models to users via UC_MODE flags (#1165) 2020-01-14 09:37:21 -05:00
include osdep.h: Drop no-longer-needed Coverity workarounds 2020-04-30 07:27:24 -04:00
qapi qapi: Rewrite string-input-visitor's integer and list parsing 2018-12-18 04:57:25 -05:00
qobject qstring: Move qstring_from_substr()'s @end one to the right 2018-08-02 21:24:19 -04:00
qom cpu: Move icount_decr to CPUNegativeOffsetState 2019-06-13 15:34:28 -04:00
scripts decodetree: Use Python3 floor division operator 2020-04-30 07:16:30 -04:00
target riscv: Fix Stage2 SV32 page table walk 2020-04-30 20:54:08 -04:00
tcg tcg/mips: mips sync* encode error 2020-04-30 07:24:57 -04:00
util util/cutils: Turn FIXME comment into QEMU_BUILD_BUG_ON() 2020-01-14 08:04:30 -05:00
aarch64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
aarch64eb.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
accel.c clean-up: removed duplicate #includes 2018-02-28 08:51:56 -05:00
arm.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
armeb.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
CODING_STYLE.rst docs: split the CODING_STYLE doc into distinct groups 2019-11-28 02:54:44 -05:00
configure configure: Support -static-pie if requested 2020-04-30 07:09:34 -04:00
COPYING
COPYING.LIB
cpus.c Include qapi/error.h exactly where needed 2018-03-07 12:26:38 -05:00
exec.c Memory: Enable writeback for given memory region 2020-01-14 07:44:24 -05:00
gen_all_header.sh
glib_compat.c target/arm: Add VHE system register redirection and aliasing 2020-03-21 15:57:03 -04:00
header_gen.py header_gen: Add gen_{u,s}shl_i{32,64} to arm 2020-04-13 19:38:59 +01:00
ioport.c hw: remove pio_addr_t 2018-02-24 02:43:16 -05:00
LICENSE
m68k.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
Makefile Makefile: Rename targets for make recursion 2019-08-08 17:26:49 -04:00
Makefile.objs qapi: Move qapi-schema.json to qapi/, rename generated files 2018-03-09 11:35:11 -05:00
Makefile.target configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012] 2018-12-18 03:52:36 -05:00
memory.c Memory: Enable writeback for given memory region 2020-01-14 07:44:24 -05:00
memory_ldst.inc.c memory: Single byte swap along the I/O path 2020-01-07 19:12:04 -05:00
memory_mapping.c include/qemu/osdep.h: Don't include qapi/error.h 2018-02-21 23:08:18 -05:00
mips.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
mips64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
mips64el.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
mipsel.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
powerpc.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
qemu-timer.c timer/cpus: fix some typos and update some comments 2018-02-25 23:21:57 -05:00
riscv32.h target/riscv: Emulate TIME CSRs for privileged mode 2020-03-22 02:22:17 -04:00
riscv64.h target/riscv: Emulate TIME CSRs for privileged mode 2020-03-22 02:22:17 -04:00
rules.mak build-sys: silence make by default or V=0 2018-03-06 08:58:03 -05:00
sparc.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
sparc64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
unicorn_common.h unicorn_common: Fix unicorn memory functions failing 2018-09-03 10:40:14 -04:00
VERSION Open 5.1 development tree 2020-04-30 07:30:38 -04:00
vl.c Use cpu_create(type) instead of cpu_init(cpu_model) 2018-03-20 14:20:30 -04:00
vl.h
x86_64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00