Anup Patel 15e558e9cc riscv: Fix Stage2 SV32 page table walk ... As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has 12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1] is required to handle the 34bit intermediate physical address coming from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2 SV32 level-0 page table will be 16KB in size with total 4096 enteries where each entry maps 4MB of memory (same as Stage1 SV32 page table). The get_physical_address() function is broken for Stage2 SV32 level-0 page table because it incorrectly computes output physical address for Stage2 SV32 level-0 page table entry. The root cause of the issue is that get_physical_address() uses the "widened" variable to compute level-0 physical address mapping which changes level-0 mapping size (instead of 4MB). We should use the "widened" variable only for computing index of Stage2 SV32 level-0 page table. Backports commit ee79e7cd47ef47074d7c20c221321c5d31d3683d from qemu		2020-04-30 20:54:08 -04:00
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arm	target/arm: Fix ID_MMFR4 value on AArch64 'max' CPU	2020-04-30 07:29:06 -04:00
i386	various: Remove suspicious '\' character outside of #define in C code	2020-04-30 07:31:45 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/mips: Fix loongson multimedia condition instructions	2020-04-30 07:14:10 -04:00
riscv	riscv: Fix Stage2 SV32 page table walk	2020-04-30 20:54:08 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00