Paul Burton 1c6732b053 atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32 ... ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for all MIPS host builds, including those using the n32 ABI. n32 is the MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU for an n32 host with support for a 64b target architecture then TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various atomic_* functions to generate errors. Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we already do for x86_64/x32. Backports commit c5b00c1684f3317e887c7401b58dde54c2b05354 from qemu		2019-01-05 07:26:14 -05:00
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crypto	Drop unused crypto source files	2018-02-17 15:23:57 -05:00
exec	tcg: Add TCG_CALL_NO_RETURN	2019-01-05 06:35:21 -05:00
fpu	softfloat: add float{32,64}_is_zero_or_normal	2018-12-19 10:31:10 -05:00
hw	Use cpu_create(type) instead of cpu_init(cpu_model)	2018-03-20 14:20:30 -04:00
qapi	qapi: Rewrite string-input-visitor's integer and list parsing	2018-12-18 04:57:25 -05:00
qemu	atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32	2019-01-05 07:26:14 -05:00
qom	move ObjectClass to typedefs.h	2018-12-11 20:37:04 -05:00
sysemu	tcg: add options for enabling MTTCG	2018-03-02 09:25:01 -05:00
config.h	import	2015-08-21 15:04:50 +08:00
elf.h	include/elf: Update elf.h to commit f71a8eaffba3271cf7cdad95572f6996f7523a5b	2018-03-11 15:34:35 -04:00
glib_compat.h	Use cpu_create(type) instead of cpu_init(cpu_model)	2018-03-20 14:20:30 -04:00
qemu-common.h	tcg: Add EXCP_ATOMIC	2018-02-27 11:57:58 -05:00