Peter Maydell 2944a75b98 target/arm: Pull handling of XScale insns out of disas_coproc_insn() ... At the moment we check for XScale/iwMMXt insns inside disas_coproc_insn(): for CPUs with ARM_FEATURE_XSCALE all copro insns with cp 0 or 1 are handled specially. This works, but is an odd place for this check, because disas_coproc_insn() is called from both the Arm and Thumb decoders but the XScale case never applies for Thumb (all the XScale CPUs were ARMv5, which has only Thumb1, not Thumb2 with the 32-bit coprocessor insn encodings). It also makes it awkward to convert the real copro access insns to decodetree. Move the identification of XScale out to its own function which is only called from disas_arm_insn(). Backports commit 7b4f933db865391a90a3b4518bb2050a83f2a873 from qemu		2021-02-26 10:50:32 -05:00
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arm	target/arm: Pull handling of XScale insns out of disas_coproc_insn()	2021-02-26 10:50:32 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: vector single-width integer multiply instructions	2021-02-26 10:46:26 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00