unicorn/qemu/target
Marc Zyngier 2e8c8b5a7c
target/arm: Fix ISR_EL1 tracking when executing at EL2
The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1,
ISR_EL1 shows the pending status of the physical IRQ, FIQ, or
SError interrupts.

Unfortunately, QEMU's implementation only considers the HCR_EL2
bits, and ignores the current exception level. This means a hypervisor
trying to look at its own interrupt state actually sees the guest
state, which is unexpected and breaks KVM as of Linux 5.3.

Instead, check for the running EL and return the physical bits
if not running in a virtualized context.

Backports commit 7cf95aed53c8770a338617ef40d5f37d2c197853 from qemu
2019-11-28 03:41:38 -05:00
..
arm target/arm: Fix ISR_EL1 tracking when executing at EL2 2019-11-28 03:41:38 -05:00
i386 tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
m68k tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
mips tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
riscv tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
sparc tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00