unicorn/qemu/target/riscv
Tony Nguyen f75368cd0f
tcg: TCGMemOp is now accelerator independent MemOp
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Backports commit 14776ab5a12972ea439c7fb2203a4c15a09094b4 from qemu
2019-11-28 03:01:12 -05:00
..
insn_trans tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 19:35:46 -04:00
cpu.c target/riscv: rationalise softfloat includes 2019-11-18 21:17:03 -05:00
cpu.h target/riscv: rationalise softfloat includes 2019-11-18 21:17:03 -05:00
cpu_bits.h target/riscv: Add the mcountinhibit CSR 2019-08-08 17:04:52 -04:00
cpu_helper.c RISC-V: Clear load reservations on context switch and SC 2019-08-08 17:15:45 -04:00
cpu_user.h Supply missing header guards 2019-06-12 10:59:10 -04:00
csr.c RISC-V: Add support for the Zicsr extension 2019-08-08 17:10:34 -04:00
fpu_helper.c target/riscv: rationalise softfloat includes 2019-11-18 21:17:03 -05:00
helper.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-28 19:20:36 -04:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-28 19:20:36 -04:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
insn32.decode target/riscv: Name the argument sets for all of insn32 formats 2019-05-28 18:36:53 -04:00
instmap.h Supply missing header guards 2019-06-12 10:59:10 -04:00
Makefile.objs target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
op_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-12 12:06:19 -04:00
pmp.c RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off 2019-08-08 16:55:52 -04:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-08-08 16:52:57 -04:00
translate.c target/riscv: Remove redundant declaration pragmas 2019-11-18 21:22:09 -05:00
unicorn.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
unicorn.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00