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RISC-V: Add support for the Zicsr extension

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The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.

Backports commit 591bddea8d874e1500921de0353818e5586618f5 from qemu
This commit is contained in:
Palmer Dabbelt 2019-08-08 17:10:32 -04:00 committed by Lioncash
parent 5b59f956b3
commit 4a3d8417ca
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 7 additions and 0 deletions
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1
qemu/target/riscv/cpu.h
View file

@ -224,6 +224,7 @@ typedef struct RISCVCPU {
struct {
bool ext_ifencei;
bool ext_icsr;
} cfg;
} RISCVCPU;

6
qemu/target/riscv/csr.c
View file

@ -797,6 +797,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
{
int ret;
target_ulong old_value;
RISCVCPU *cpu = env_archcpu(env);
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
@ -807,6 +808,11 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
return -1;
}
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
return -1;