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unicorn/qemu/target/riscv/insn_trans
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Ian Jiang 5c3a2f391c riscv: Add helper to make NaN-boxing for FP register 
The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.

Backports commit 354908cee1f7ff761b5fedbdb6376c378c10f941 from qemu
2021-02-25 11:53:27 -05:00
..
trans_privileged.inc.c target/riscv: Drop support for ISA spec version 1.09.1 2020-06-14 22:23:26 -04:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvd.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-03-21 12:20:52 -04:00
trans_rvf.inc.c riscv: Add helper to make NaN-boxing for FP register 2021-02-25 11:53:27 -05:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00