Richard Henderson 3af34d3df4 target/riscv: Check nanboxed inputs in trans_rvf.inc.c ... If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. The only inline expansion is for the sign-changing set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S. Backports ffe70e4dfc9cf2a6934e674b81b69c847b403c4b		2021-03-08 12:38:15 -05:00
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arm	target/arm/cpu: Update coding style to make checkpatch.pl happy	2021-03-08 11:35:28 -05:00
i386	i386: Fix build	2021-03-05 08:35:14 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Check nanboxed inputs in trans_rvf.inc.c	2021-03-08 12:38:15 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00