Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, X86)
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Peter Maydell 44bf8985e5
arm: Implement M profile exception return properly
On M profile, return from exceptions happen when code in Handler mode
executes one of the following function call return instructions:
* POP or LDM which loads the PC
* LDR to PC
* BX register
and the new PC value is 0xFFxxxxxx.

QEMU tries to implement this by not treating the instruction
specially but then catching the attempt to execute from the magic
address value. This is not ideal, because:
* there are guest visible differences from the architecturally
specified behaviour (for instance jumping to 0xFFxxxxxx via a
different instruction should not cause an exception return but it
will in the QEMU implementation)
* we have to account for it in various places (like refusing to take
an interrupt if the PC is at a magic value, and making sure that
the MPU doesn't deny execution at the magic value addresses)

Drop these hacks, and instead implement exception return the way the
architecture specifies -- by having the relevant instructions check
for the magic value and raise the 'do an exception return' QEMU
internal exception immediately.

The effect on the generated code is minor:

bx lr, old code (and new code for Thread mode):
TCG:
mov_i32 tmp5,r14
movi_i32 tmp6,$0xfffffffffffffffe
and_i32 pc,tmp5,tmp6
movi_i32 tmp6,$0x1
and_i32 tmp5,tmp5,tmp6
st_i32 tmp5,env,$0x218
exit_tb $0x0
set_label $L0
exit_tb $0x7f2aabd61993
x86_64 generated code:
0x7f2aabe87019: mov %ebx,%ebp
0x7f2aabe8701b: and $0xfffffffffffffffe,%ebp
0x7f2aabe8701e: mov %ebp,0x3c(%r14)
0x7f2aabe87022: and $0x1,%ebx
0x7f2aabe87025: mov %ebx,0x218(%r14)
0x7f2aabe8702c: xor %eax,%eax
0x7f2aabe8702e: jmpq 0x7f2aabe7c016

bx lr, new code when in Handler mode:
TCG:
mov_i32 tmp5,r14
movi_i32 tmp6,$0xfffffffffffffffe
and_i32 pc,tmp5,tmp6
movi_i32 tmp6,$0x1
and_i32 tmp5,tmp5,tmp6
st_i32 tmp5,env,$0x218
movi_i32 tmp5,$0xffffffffff000000
brcond_i32 pc,tmp5,geu,$L1
exit_tb $0x0
set_label $L1
movi_i32 tmp5,$0x8
call exception_internal,$0x0,$0,env,tmp5
x86_64 generated code:
0x7fe8fa1264e3: mov %ebp,%ebx
0x7fe8fa1264e5: and $0xfffffffffffffffe,%ebx
0x7fe8fa1264e8: mov %ebx,0x3c(%r14)
0x7fe8fa1264ec: and $0x1,%ebp
0x7fe8fa1264ef: mov %ebp,0x218(%r14)
0x7fe8fa1264f6: cmp $0xff000000,%ebx
0x7fe8fa1264fc: jae 0x7fe8fa126509
0x7fe8fa126502: xor %eax,%eax
0x7fe8fa126504: jmpq 0x7fe8fa122016
0x7fe8fa126509: mov %r14,%rdi
0x7fe8fa12650c: mov $0x8,%esi
0x7fe8fa126511: mov $0x56095dbeccf5,%r10
0x7fe8fa12651b: callq *%r10

which is a difference of one cmp/branch-not-taken. This will
be lost in the noise of having to exit generated code and
look up the next TB anyway.

Backports commit 3bb8a96f5348913ee130169504f3642f501b113e from qemu
2018-03-02 14:58:14 -05:00
bindings link to Crystal binding 2017-12-23 00:26:40 +08:00
docs Added note about installing tests dependencies on Mac OS X. Added note about tests failing when required architecture support is disabled in build. (#908) 2017-10-12 19:56:00 +08:00
include tcg: remove global exit_request 2018-03-02 09:38:08 -05:00
msvc tcg: move TCG_MO/BAR types into own file 2018-03-02 09:08:44 -05:00
qemu arm: Implement M profile exception return properly 2018-03-02 14:58:14 -05:00
samples Fixed register mistake in comments (#894) 2017-09-17 16:40:01 +07:00
tests add 64-bit test demonstrating setting MSRs and FS/GS segments (#901) 2017-09-29 04:26:23 +08:00
.appveyor.yml MSYS test (#852) 2017-06-25 10:11:35 +08:00
.gitignore arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
.travis.yml use new travis osx image and brew (#935) 2018-01-05 10:29:49 +08:00
AUTHORS.TXT import 2015-08-21 15:04:50 +08:00
Brewfile Update Brewfile 2017-09-30 17:36:44 +07:00
ChangeLog update ChangeLog 2017-04-20 13:28:02 +08:00
config.mk Fix document file extension 2016-08-08 17:33:49 +09:00
COPYING import 2015-08-21 15:04:50 +08:00
COPYING.LGPL2 LGPL2 for all header files under include/unicorn/ 2017-12-16 10:08:42 +08:00
COPYING_GLIB glib_compat: add COPYING_GLIB 2016-12-27 10:15:08 +08:00
CREDITS.TXT update CREDITS.TXT 2017-04-25 12:56:47 +08:00
install-cmocka-linux.sh Start moving examples in S files (#851) 2017-06-25 10:14:22 +08:00
list.c callback to count number of instructions in uc_emu_start() should be executed first. fix #727 2017-06-16 13:22:38 +08:00
make.sh Added MSVC support for arm64eb. 2017-04-25 14:23:58 +10:00
Makefile crypto: introduce new module for computing hash digests 2018-02-17 15:23:17 -05:00
msvc.bat add msvc.bat 2017-04-21 15:35:40 +08:00
pkgconfig.mk bump extra version to 2 2017-04-21 15:30:40 +08:00
README.md add Clojure 2017-12-23 00:32:33 +08:00
uc.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
windows_export.bat Make the call out to visual studio extremely resilient 2017-01-02 03:32:48 -08:00

Unicorn Engine

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Build Status Build status

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

  • Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
  • Clean/simple/lightweight/intuitive architecture-neutral API
  • Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
  • Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
  • High performance via Just-In-Time compilation
  • Support for fine-grained instrumentation at various levels
  • Thread-safety by design
  • Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contact us via mailing list, email or twitter for any questions.

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.