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unicorn/qemu/target-mips
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Yongbok Kim 4544aa4134
target-mips: Set Config5.XNP for R6 cores 
Set Config5.XNP for R6 cores to indicate the extended LL/SC family
of instructions NOT present.

Backports commit 35ac9e342e008e3d47ef18d33a6977fdb99de9cd from qemu
2018-02-17 15:24:13 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c target-mips: implement the CPU wake-up on non-enabled interrupts in R6 2018-02-17 15:24:12 -05:00
cpu.h target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
dsp_helper.c Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
helper.c target-mips: move the test for enabled interrupts to a separate function 2018-02-17 15:24:12 -05:00
helper.h target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
lmi_helper.c import 2015-08-21 15:04:50 +08:00
Makefile.objs import 2015-08-21 15:04:50 +08:00
mips-defs.h target-mips: fix MIPS64R6-generic configuration 2018-02-17 15:23:21 -05:00
msa_helper.c target-mips: improve exception handling 2018-02-17 15:23:53 -05:00
op_helper.c target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
TODO import 2015-08-21 15:04:50 +08:00
translate.c target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
translate_init.c target-mips: Set Config5.XNP for R6 cores 2018-02-17 15:24:13 -05:00
unicorn.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
unicorn.h armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00