Richard Henderson 49cb8cfe5b target/mips: Tidy control flow in mips_cpu_handle_mmu_fault ... Since the only non-negative TLBRET_* value is TLBRET_MATCH, the subsequent test for ret < 0 is useless. Use early return to allow subsequent blocks to be unindented. Backports commit e38f4eb63020075432cb77bf48398187809cf4a3 from qemu		2019-05-16 17:15:33 -04:00
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cp0_timer.c	mips: introduce internal.h and cleanup cpu.h	2018-03-05 00:25:56 -05:00
cpu-qom.h	mips: MIPSCPU model subclasses	2018-03-05 00:42:29 -05:00
cpu.c	target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()	2018-09-03 17:36:23 -04:00
cpu.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
dsp_helper.c	mips: Improve macro parenthesization	2018-03-05 00:51:51 -05:00
helper.c	target/mips: Tidy control flow in mips_cpu_handle_mmu_fault	2019-05-16 17:15:33 -04:00
helper.h	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
internal.h	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	2019-01-22 19:51:38 -05:00
lmi_helper.c	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
Makefile.objs	mips: introduce internal.h and cleanup cpu.h	2018-03-05 00:25:56 -05:00
mips-defs.h	target/mips: Define a bit for MXU in insn_flags	2018-11-11 05:52:18 -05:00
msa_helper.c	target/mips: Remove floatX_maybe_silence_nan from conversions	2018-05-19 23:25:04 -04:00
op_helper.c	target/mips: reimplement SC instruction emulation and use cmpxchg	2019-02-15 17:10:16 -05:00
TODO	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
translate.c	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00
translate_init.c	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
unicorn.c	Use DEFINE_MACHINE() to register all machines	2018-03-11 15:12:46 -04:00
unicorn.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00