Palmer Dabbelt 4a3d8417ca RISC-V: Add support for the Zicsr extension ... The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Backports commit 591bddea8d874e1500921de0353818e5586618f5 from qemu		2019-08-08 17:10:34 -04:00
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arm	target/arm: Declare some M-profile functions publicly	2019-08-08 15:37:01 -04:00
i386	target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY	2019-06-25 18:59:52 -05:00
m68k	m68k comments break patch submission due to being incorrectly formatted	2019-08-08 14:26:45 -04:00
mips	target/mips: Correct helper for MSA FCLASS.<W|D> instructions	2019-08-08 16:30:15 -04:00
riscv	RISC-V: Add support for the Zicsr extension	2019-08-08 17:10:34 -04:00
sparc	cpu: Introduce CPUNegativeOffsetState	2019-06-13 15:08:25 -04:00