LIU Zhiwei 4b1e548fd0 target/riscv: vector single-width integer reduction instructions ... Backports fe5c9ab1fc185e96bf7e034954127429ca74d386		2021-03-07 12:07:51 -05:00
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trans_privileged.inc.c	target/riscv: Move the hfence instructions to the rvh decode	2021-02-25 11:59:49 -05:00
trans_rva.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
trans_rvd.inc.c	target/riscv: fsd/fsw doesn't dirty FP state	2020-03-21 12:20:52 -04:00
trans_rvf.inc.c	riscv: Add helper to make NaN-boxing for FP register	2021-02-25 11:53:27 -05:00
trans_rvh.inc.c	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
trans_rvi.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00
trans_rvv.inc.c	target/riscv: vector single-width integer reduction instructions	2021-03-07 12:07:51 -05:00