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unicorn/qemu/target/arm
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Peter Maydell 68f645dd4f target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns 
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Backports e4d51ac6921dc861bfb3d20e4c7dcf345840a9da
2021-03-03 20:17:20 -05:00
..
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
arm-powerctl.c arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() 2020-01-07 18:10:29 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
cpu-param.h target/arm: Don't use a TLB for ARMMMUIdx_Stage2 2020-05-07 08:40:06 -04:00
cpu-qom.h arm: Fix typo in AARCH64_CPU_GET_CLASS definition 2021-03-01 18:03:29 -05:00
cpu.c target/arm: Implement Cortex-M55 model 2021-03-03 20:06:06 -05:00
cpu.h target/arm: add aarch32 ID register fields to cpu.h 2021-03-03 20:16:26 -05:00
cpu64.c target/arm: enable Small Translation tables in max CPU 2021-03-03 20:11:10 -05:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
debug_helper.c target/arm: Stop assuming DBGDIDR always exists 2020-03-21 18:26:24 -04:00
helper-a64.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
helper-a64.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
helper-sve.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
helper.c target/arm: ARMv8.4-TTST extension 2021-03-03 20:09:01 -05:00
helper.h target/arm: Fix neon VTBL/VTBX for len > 1 2021-03-02 13:23:13 -05:00
internals.h target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11 2021-03-01 20:12:36 -05:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
m-nocp.decode target/arm: Implement new v8.1M VLLDM and VLSTM encodings 2021-03-03 19:01:33 -05:00
m_helper.c target/arm: Implement CCR_S.TRD behaviour for SG insns 2021-03-03 19:05:25 -05:00
Makefile.objs target/arm: Do M-profile NOCP checks early and via decodetree 2021-02-26 11:17:23 -05:00
mte_helper.c target/arm: Fix reported EL for mte_check_fail 2021-03-01 20:10:44 -05:00
neon-dp.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
neon-ls.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
neon-shared.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
neon_helper.c target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree 2020-05-15 23:26:51 -04:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
pauth_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
psci.c fix WFI/WFE length in syndrome register 2018-03-05 11:21:51 -05:00
sve.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
sve_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
t32.decode target/arm: Implement M-profile "minimal RAS implementation" 2021-03-03 19:07:27 -05:00
tlb_helper.c target/arm: Cache the Tagged bit for a page in MemTxAttrs 2021-02-25 22:48:04 -05:00
translate-a64.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
translate-a64.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
translate-neon.inc.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
translate-sve.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
translate-vfp.inc.c target/arm: Implement FPCXT_NS fp system register 2021-03-03 20:02:36 -05:00
translate.c target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns 2021-03-03 20:17:20 -05:00
translate.h target/arm: Rearrange {sve,fp}_check_access assert 2021-02-26 13:56:27 -05:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
unicorn_arm.c arm/translate: Do not tracecode when in an IT block 2021-02-07 19:14:32 +00:00
vec_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
vec_internal.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
vfp.decode target/arm: Implement VLDR/VSTR system register 2021-03-03 18:42:05 -05:00
vfp_helper.c target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension 2021-03-01 20:36:02 -05:00