Hou Weiying 55be7adad9 riscv: Fix bug in setting pmpcfg CSR for RISCV64 ... First, sizeof(target_ulong) equals to 4 on riscv32, so this change does not change the function on riscv32. Second, sizeof(target_ulong) equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal pmp_index (we will explain later), which should be 'reg_index * 4 + i'. If the parameter reg_index equals to 2 (means that we will change the value of pmpcfg2, or the second pmpcfg on riscv64), then pmpcfg_csr_write(env, 2, val) will map write tasks to pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed by value 16 or 23 on riscv64, so we consider it as a bug. We are looking for constant (e.g., define a new constant named RISCV_WORD_SIZE) in QEMU to help others understand code better, but none was found. A possible good explanation of this literal is it is the minimum word length on riscv is 4 bytes (32 bit). Backports fdd33b86b20d153b131fc6259aea7a0084ab14b8		2021-03-08 12:42:12 -05:00
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arm	target/arm/cpu: Update coding style to make checkpatch.pl happy	2021-03-08 11:35:28 -05:00
i386	i386: Fix build	2021-03-05 08:35:14 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	riscv: Fix bug in setting pmpcfg CSR for RISCV64	2021-03-08 12:42:12 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00