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5c41e8e7ed
Add the ARM Cortex-A53 processor definition. Similar to A57, but with different L1 I cache policy, phys addr size and different cache geometries. The cache sizes is implementation configurable, but use these values (from Xilinx Zynq MPSoC) as a default until cache size configurability is added. Backports commit e35310260ec57d20301c65a5714ca55369e971cc from qemu |
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arm_ldst.h | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
cpu64.c | ||
crypto_helper.c | ||
helper-a64.c | ||
helper-a64.h | ||
helper.c | ||
helper.h | ||
internals.h | ||
iwmmxt_helper.c | ||
kvm-consts.h | ||
Makefile.objs | ||
neon_helper.c | ||
op_addsub.h | ||
op_helper.c | ||
psci.c | ||
translate-a64.c | ||
translate.c | ||
translate.h | ||
unicorn.h | ||
unicorn_aarch64.c | ||
unicorn_arm.c |