Peter Maydell 60ccaf56ac target/arm/translate-a64: Don't underdecode SIMD ld/st multiple ... In the AdvSIMD load/store multiple structures encodings, the non-post-indexed case should have zeroes in [20:16] (which is the Rm field for the post-indexed case). Correctly UNDEF the currently unallocated encodings which have non-zeroes in those bits. Backports commit e1f220811dbd5d85fb02ff286358f9ee6188938f from qemu		2019-02-03 17:55:29 -05:00
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arm	target/arm/translate-a64: Don't underdecode SIMD ld/st multiple	2019-02-03 17:55:29 -05:00
i386	i386: Enable NPT and NRIPSAVE for AMD CPUs	2019-02-03 17:55:28 -05:00
m68k	target/m68k: Fix LGPL information in the file headers	2019-02-03 17:55:29 -05:00
mips	target/mips: Add I6500 core configuration	2019-01-25 13:46:18 -05:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00