Hesham Almatary 614c2954b0 RISC-V: Check for the effective memory privilege mode during PMP checks ... The current PMP check function checks for env->priv which is not the effective memory privilege mode. For example, mstatus.MPRV could be set while executing in M-Mode, and in that case the privilege mode for the PMP check should be S-Mode rather than M-Mode (in env->priv) if mstatus.MPP == PRV_S. This patch passes the effective memory privilege mode to the PMP check. Functions that call the PMP check should pass the correct memory privilege mode after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists). Backports commit cc0fdb298517ce56c770803447f8b02a90271152 from qemu		2019-08-08 16:52:57 -04:00
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arm	target/arm: Declare some M-profile functions publicly	2019-08-08 15:37:01 -04:00
i386	target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY	2019-06-25 18:59:52 -05:00
m68k	m68k comments break patch submission due to being incorrectly formatted	2019-08-08 14:26:45 -04:00
mips	target/mips: Correct helper for MSA FCLASS.<W|D> instructions	2019-08-08 16:30:15 -04:00
riscv	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-08-08 16:52:57 -04:00
sparc	cpu: Introduce CPUNegativeOffsetState	2019-06-13 15:08:25 -04:00