mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-25 00:45:30 +00:00
187778c781
Cleanup in the boilerplate that each target must define. Replace x86_env_get_cpu with env_archcpu. The combination CPU(x86_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 6aa9e42f27331be34e06d4d66f92f2272868f96a from qemu
848 lines
25 KiB
C
848 lines
25 KiB
C
/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/sysemu.h"
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#endif
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void cpu_sync_bndcs_hflags(CPUX86State *env)
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{
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uint32_t hflags = env->hflags;
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uint32_t hflags2 = env->hflags2;
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uint32_t bndcsr;
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if ((hflags & HF_CPL_MASK) == 3) {
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bndcsr = env->bndcs_regs.cfgu;
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} else {
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bndcsr = env->msr_bndcfgs;
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}
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if ((env->cr[4] & CR4_OSXSAVE_MASK)
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&& (env->xcr0 & XSTATE_BNDCSR_MASK)
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&& (bndcsr & BNDCFG_ENABLE)) {
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hflags |= HF_MPX_EN_MASK;
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} else {
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hflags &= ~HF_MPX_EN_MASK;
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}
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if (bndcsr & BNDCFG_BNDPRESERVE) {
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hflags2 |= HF2_MPX_PR_MASK;
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} else {
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hflags2 &= ~HF2_MPX_PR_MASK;
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}
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env->hflags = hflags;
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env->hflags2 = hflags2;
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}
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static void cpu_x86_version(CPUX86State *env, int *family, int *model)
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{
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int cpuver = env->cpuid_version;
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if (family == NULL || model == NULL) {
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return;
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}
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*family = (cpuver >> 8) & 0x0f;
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*model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
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}
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/* Broadcast MCA signal for processor version 06H_EH and above */
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int cpu_x86_support_mca_broadcast(CPUX86State *env)
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{
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int family = 0;
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int model = 0;
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cpu_x86_version(env, &family, &model);
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if ((family == 6 && model >= 14) || family > 6) {
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return 1;
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}
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return 0;
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}
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/***********************************************************/
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/* x86 debug */
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static const char *cc_op_str[CC_OP_NB] = {
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"DYNAMIC",
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"EFLAGS",
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"MULB",
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"MULW",
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"MULL",
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"MULQ",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADDQ",
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"ADCB",
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"ADCW",
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"ADCL",
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"ADCQ",
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"SUBB",
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"SUBW",
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"SUBL",
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"SUBQ",
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"SBBB",
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"SBBW",
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"SBBL",
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"SBBQ",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"LOGICQ",
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"INCB",
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"INCW",
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"INCL",
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"INCQ",
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"DECB",
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"DECW",
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"DECL",
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"DECQ",
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"SHLB",
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"SHLW",
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"SHLL",
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"SHLQ",
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"SARB",
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"SARW",
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"SARL",
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"SARQ",
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"BMILGB",
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"BMILGW",
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"BMILGL",
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"BMILGQ",
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"ADCX",
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"ADOX",
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"ADCOX",
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"CLR",
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};
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static void
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cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, fprintf_function cpu_fprintf,
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const char *name, struct SegmentCache *sc)
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{
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
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sc->selector, sc->base, sc->limit, sc->flags & 0x00ffff00);
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} else
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#endif
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{
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cpu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
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(uint32_t)sc->base, sc->limit, sc->flags & 0x00ffff00);
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}
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if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
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goto done;
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cpu_fprintf(f, " DPL=%d ", (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
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if (sc->flags & DESC_S_MASK) {
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if (sc->flags & DESC_CS_MASK) {
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cpu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
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((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
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cpu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
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(sc->flags & DESC_R_MASK) ? 'R' : '-');
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} else {
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cpu_fprintf(f,
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(sc->flags & DESC_B_MASK || env->hflags & HF_LMA_MASK)
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? "DS " : "DS16");
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cpu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
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(sc->flags & DESC_W_MASK) ? 'W' : '-');
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}
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cpu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
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} else {
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static const char *sys_type_name[2][16] = {
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{ /* 32 bit mode */
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"Reserved", "TSS16-avl", "LDT", "TSS16-busy",
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"CallGate16", "TaskGate", "IntGate16", "TrapGate16",
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"Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
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"CallGate32", "Reserved", "IntGate32", "TrapGate32"
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},
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{ /* 64 bit mode */
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"<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
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"Reserved", "Reserved", "Reserved", "Reserved",
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"TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
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"Reserved", "IntGate64", "TrapGate64"
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}
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};
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cpu_fprintf(f, "%s",
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sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
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[(sc->flags & DESC_TYPE_MASK)
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>> DESC_TYPE_SHIFT]);
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}
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done:
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cpu_fprintf(f, "\n");
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}
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#define DUMP_CODE_BYTES_TOTAL 50
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#define DUMP_CODE_BYTES_BACKWARD 20
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void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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X86CPU *cpu = X86_CPU(cs->uc, cs);
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CPUX86State *env = &cpu->env;
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int eflags, i, nb;
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char cc_op_name[32];
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
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eflags = cpu_compute_eflags(env);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f,
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"RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
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"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
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"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
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"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
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"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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env->regs[R_EAX],
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env->regs[R_EBX],
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env->regs[R_ECX],
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env->regs[R_EDX],
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env->regs[R_ESI],
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env->regs[R_EDI],
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env->regs[R_EBP],
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env->regs[R_ESP],
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env->regs[8],
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env->regs[9],
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env->regs[10],
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env->regs[11],
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env->regs[12],
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env->regs[13],
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env->regs[14],
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env->regs[15],
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env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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cs->halted);
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} else
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#endif
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{
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cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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(uint32_t)env->regs[R_EAX],
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(uint32_t)env->regs[R_EBX],
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(uint32_t)env->regs[R_ECX],
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(uint32_t)env->regs[R_EDX],
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(uint32_t)env->regs[R_ESI],
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(uint32_t)env->regs[R_EDI],
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(uint32_t)env->regs[R_EBP],
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(uint32_t)env->regs[R_ESP],
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(uint32_t)env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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cs->halted);
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}
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for(i = 0; i < 6; i++) {
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cpu_x86_dump_seg_cache(env, f, cpu_fprintf, seg_name[i],
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&env->segs[i]);
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}
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cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "LDT", &env->ldt);
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cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
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env->gdt.base, env->gdt.limit);
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cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
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env->idt.base, env->idt.limit);
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cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
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(uint32_t)env->cr[0],
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env->cr[2],
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env->cr[3],
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(uint32_t)env->cr[4]);
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for(i = 0; i < 4; i++)
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cpu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
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cpu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
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env->dr[6], env->dr[7]);
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} else
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#endif
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{
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cpu_fprintf(f, "GDT= %08x %08x\n",
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(uint32_t)env->gdt.base, env->gdt.limit);
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cpu_fprintf(f, "IDT= %08x %08x\n",
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(uint32_t)env->idt.base, env->idt.limit);
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cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
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(uint32_t)env->cr[0],
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(uint32_t)env->cr[2],
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(uint32_t)env->cr[3],
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(uint32_t)env->cr[4]);
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for(i = 0; i < 4; i++) {
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cpu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
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}
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cpu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
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env->dr[6], env->dr[7]);
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}
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if (flags & CPU_DUMP_CCOP) {
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if ((unsigned)env->cc_op < CC_OP_NB)
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snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
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else
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
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env->cc_src, env->cc_dst,
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cc_op_name);
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} else
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#endif
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{
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cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
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(uint32_t)env->cc_src, (uint32_t)env->cc_dst,
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cc_op_name);
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}
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}
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cpu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
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if (flags & CPU_DUMP_FPU) {
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int fptag;
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fptag = 0;
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for(i = 0; i < 8; i++) {
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fptag |= ((!env->fptags[i]) << i);
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}
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cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
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env->fpuc,
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(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
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env->fpstt,
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fptag,
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env->mxcsr);
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for(i=0;i<8;i++) {
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CPU_LDoubleU u;
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u.d = env->fpregs[i].d;
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cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
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i, u.l.lower, u.l.upper);
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if ((i & 1) == 1)
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cpu_fprintf(f, "\n");
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else
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cpu_fprintf(f, " ");
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}
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if (env->hflags & HF_CS64_MASK)
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nb = 16;
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else
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nb = 8;
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for(i=0;i<nb;i++) {
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cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
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i,
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env->xmm_regs[i].ZMM_L(3),
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env->xmm_regs[i].ZMM_L(2),
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env->xmm_regs[i].ZMM_L(1),
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env->xmm_regs[i].ZMM_L(0));
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if ((i & 1) == 1)
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cpu_fprintf(f, "\n");
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else
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cpu_fprintf(f, " ");
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}
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}
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if (flags & CPU_DUMP_CODE) {
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target_ulong base = env->segs[R_CS].base + env->eip;
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target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
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uint8_t code;
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char codestr[3];
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cpu_fprintf(f, "Code=");
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for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
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if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
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snprintf(codestr, sizeof(codestr), "%02x", code);
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} else {
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snprintf(codestr, sizeof(codestr), "??");
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}
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cpu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
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i == offs ? "<" : "", codestr, i == offs ? ">" : "");
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}
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cpu_fprintf(f, "\n");
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}
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}
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|
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/***********************************************************/
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/* x86 mmu */
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/* XXX: add PGE support */
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|
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void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
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{
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CPUX86State *env = &cpu->env;
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a20_state = (a20_state != 0);
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if (a20_state != ((env->a20_mask >> 20) & 1)) {
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CPUState *cs = CPU(cpu);
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#if defined(DEBUG_MMU)
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printf("A20 update: a20=%d\n", a20_state);
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#endif
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/* if the cpu is currently executing code, we must unlink it and
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all the potentially executing TB */
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cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
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|
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/* when a20 is changed, all the MMU mappings are invalid, so
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we must flush everything */
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tlb_flush(cs);
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env->a20_mask = ~(1 << 20) | (a20_state << 20);
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}
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}
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|
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
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{
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X86CPU *cpu = env_archcpu(env);
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int pe_state;
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|
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#if defined(DEBUG_MMU)
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printf("CR0 update: CR0=0x%08x\n", new_cr0);
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#endif
|
|
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
|
|
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
|
|
tlb_flush(CPU(cpu));
|
|
}
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
|
|
(env->efer & MSR_EFER_LME)) {
|
|
/* enter in long mode */
|
|
/* XXX: generate an exception */
|
|
if (!(env->cr[4] & CR4_PAE_MASK))
|
|
return;
|
|
env->efer |= MSR_EFER_LMA;
|
|
env->hflags |= HF_LMA_MASK;
|
|
} else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
|
|
(env->efer & MSR_EFER_LMA)) {
|
|
/* exit long mode */
|
|
env->efer &= ~MSR_EFER_LMA;
|
|
env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
|
|
env->eip &= 0xffffffff;
|
|
}
|
|
#endif
|
|
env->cr[0] = new_cr0 | CR0_ET_MASK;
|
|
|
|
/* update PE flag in hidden flags */
|
|
pe_state = (env->cr[0] & CR0_PE_MASK);
|
|
env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
|
|
/* ensure that ADDSEG is always set in real mode */
|
|
env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
|
|
/* update FPU flags */
|
|
env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
|
|
((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
|
|
}
|
|
|
|
/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
|
|
the PDPT */
|
|
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
|
|
{
|
|
env->cr[3] = new_cr3;
|
|
if (env->cr[0] & CR0_PG_MASK) {
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
|
|
#endif
|
|
tlb_flush(env_cpu(env));
|
|
}
|
|
}
|
|
|
|
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
|
|
{
|
|
uint32_t hflags;
|
|
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
|
|
#endif
|
|
if ((new_cr4 ^ env->cr[4]) &
|
|
(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
|
|
CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
|
|
tlb_flush(env_cpu(env));
|
|
}
|
|
|
|
/* Clear bits we're going to recompute. */
|
|
hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK);
|
|
|
|
/* SSE handling */
|
|
if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
|
|
new_cr4 &= ~CR4_OSFXSR_MASK;
|
|
}
|
|
if (new_cr4 & CR4_OSFXSR_MASK) {
|
|
hflags |= HF_OSFXSR_MASK;
|
|
}
|
|
|
|
if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
|
|
new_cr4 &= ~CR4_SMAP_MASK;
|
|
}
|
|
if (new_cr4 & CR4_SMAP_MASK) {
|
|
hflags |= HF_SMAP_MASK;
|
|
}
|
|
|
|
if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
|
|
new_cr4 &= ~CR4_PKE_MASK;
|
|
}
|
|
|
|
env->cr[4] = new_cr4;
|
|
env->hflags = hflags;
|
|
|
|
cpu_sync_bndcs_hflags(env);
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs->uc, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
target_ulong pde_addr, pte_addr;
|
|
uint64_t pte;
|
|
int32_t a20_mask;
|
|
uint32_t page_offset;
|
|
int page_size;
|
|
|
|
a20_mask = x86_get_a20_mask(env);
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
pte = addr & a20_mask;
|
|
page_size = 4096;
|
|
} else if (env->cr[4] & CR4_PAE_MASK) {
|
|
target_ulong pdpe_addr;
|
|
uint64_t pde, pdpe;
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
bool la57 = env->cr[4] & CR4_LA57_MASK;
|
|
uint64_t pml5e_addr, pml5e;
|
|
uint64_t pml4e_addr, pml4e;
|
|
int32_t sext;
|
|
|
|
/* test virtual address sign extension */
|
|
sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
|
|
if (sext != 0 && sext != -1) {
|
|
return -1;
|
|
}
|
|
|
|
if (la57) {
|
|
pml5e_addr = ((env->cr[3] & ~0xfff) +
|
|
(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
|
|
pml5e = x86_ldq_phys(cs, pml5e_addr);
|
|
if (!(pml5e & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
} else {
|
|
pml5e = env->cr[3];
|
|
}
|
|
|
|
pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
|
|
(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
|
|
pml4e = x86_ldq_phys(cs, pml4e_addr);
|
|
if (!(pml4e & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
|
|
(((addr >> 30) & 0x1ff) << 3)) & a20_mask;
|
|
pdpe = x86_ldq_phys(cs, pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
if (pdpe & PG_PSE_MASK) {
|
|
page_size = 1024 * 1024 * 1024;
|
|
pte = pdpe;
|
|
goto out;
|
|
}
|
|
|
|
} else
|
|
#endif
|
|
{
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
|
a20_mask;
|
|
pdpe = x86_ldq_phys(cs, pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK))
|
|
return -1;
|
|
}
|
|
|
|
pde_addr = ((pdpe & PG_ADDRESS_MASK) +
|
|
(((addr >> 21) & 0x1ff) << 3)) & a20_mask;
|
|
pde = x86_ldq_phys(cs, pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
if (pde & PG_PSE_MASK) {
|
|
/* 2 MB page */
|
|
page_size = 2048 * 1024;
|
|
pte = pde;
|
|
} else {
|
|
/* 4 KB page */
|
|
pte_addr = ((pde & PG_ADDRESS_MASK) +
|
|
(((addr >> 12) & 0x1ff) << 3)) & a20_mask;
|
|
page_size = 4096;
|
|
pte = x86_ldq_phys(cs, pte_addr);
|
|
}
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
} else {
|
|
uint32_t pde;
|
|
|
|
/* page directory entry */
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
|
|
pde = x86_ldl_phys(cs, pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK))
|
|
return -1;
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
|
pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
|
|
page_size = 4096 * 1024;
|
|
} else {
|
|
/* page directory entry */
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
|
|
pte = x86_ldl_phys(cs, pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
page_size = 4096;
|
|
}
|
|
pte = pte & a20_mask;
|
|
}
|
|
|
|
#ifdef TARGET_X86_64
|
|
out:
|
|
#endif
|
|
pte &= PG_ADDRESS_MASK & ~(page_size - 1);
|
|
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
|
return pte | page_offset;
|
|
}
|
|
|
|
typedef struct MCEInjectionParams {
|
|
int bank;
|
|
uint64_t status;
|
|
uint64_t mcg_status;
|
|
uint64_t addr;
|
|
uint64_t misc;
|
|
int flags;
|
|
} MCEInjectionParams;
|
|
|
|
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
|
|
{
|
|
X86CPU *cpu = env_archcpu(env);
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
if (tcg_enabled(env->uc)) {
|
|
cpu_restore_state(cs, cs->mem_io_pc, false);
|
|
|
|
apic_handle_tpr_access_report(cpu->apic_state, env->eip, access);
|
|
}
|
|
}
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
|
|
target_ulong *base, unsigned int *limit,
|
|
unsigned int *flags)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
SegmentCache *dt;
|
|
target_ulong ptr;
|
|
uint32_t e1, e2;
|
|
int index;
|
|
|
|
if (selector & 0x4)
|
|
dt = &env->ldt;
|
|
else
|
|
dt = &env->gdt;
|
|
index = selector & ~7;
|
|
ptr = dt->base + index;
|
|
if ((uint32_t)(index + 7) > dt->limit
|
|
|| cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
|
|
|| cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
|
|
return 0;
|
|
|
|
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
|
|
*limit = (e1 & 0xffff) | (e2 & 0x000f0000);
|
|
if (e2 & DESC_G_MASK)
|
|
*limit = (*limit << 12) | 0xfff;
|
|
*flags = e2;
|
|
|
|
return 1;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
void do_cpu_init(X86CPU *cpu)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUX86State *env = &cpu->env;
|
|
CPUX86State *save = g_new(CPUX86State, 1);
|
|
int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
|
|
|
|
*save = *env;
|
|
|
|
cpu_reset(cs);
|
|
cs->interrupt_request = sipi;
|
|
memcpy(&env->start_init_save, &save->start_init_save,
|
|
offsetof(CPUX86State, end_init_save) -
|
|
offsetof(CPUX86State, start_init_save));
|
|
g_free(save);
|
|
|
|
apic_init_reset(env->uc, cpu->apic_state);
|
|
}
|
|
|
|
void do_cpu_sipi(X86CPU *cpu)
|
|
{
|
|
apic_sipi(cpu->apic_state);
|
|
}
|
|
#else
|
|
void do_cpu_init(X86CPU *cpu)
|
|
{
|
|
}
|
|
void do_cpu_sipi(X86CPU *cpu)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/* Frob eflags into and out of the CPU temporary format. */
|
|
|
|
void x86_cpu_exec_enter(CPUState *cs)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs->uc, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
env->df = 1 - (2 * ((env->eflags >> 10) & 1));
|
|
CC_OP = CC_OP_EFLAGS;
|
|
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
}
|
|
|
|
void x86_cpu_exec_exit(CPUState *cs)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs->uc, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
env->eflags = cpu_compute_eflags(env);
|
|
env->eflags0 = env->eflags;
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
return address_space_ldub(as, addr, attrs, NULL);
|
|
}
|
|
|
|
uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
return address_space_lduw(as, addr, attrs, NULL);
|
|
}
|
|
|
|
uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
return address_space_ldl(as, addr, attrs, NULL);
|
|
}
|
|
|
|
uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
return address_space_ldq(as, addr, attrs, NULL);
|
|
}
|
|
|
|
void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
address_space_stb(as, addr, val, attrs, NULL);
|
|
}
|
|
|
|
void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
address_space_stl_notdirty(as, addr, val, attrs, NULL);
|
|
}
|
|
|
|
void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
address_space_stw(as, addr, val, attrs, NULL);
|
|
}
|
|
|
|
void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
address_space_stl(as, addr, val, attrs, NULL);
|
|
}
|
|
|
|
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(NULL, cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
address_space_stq(as, addr, val, attrs, NULL);
|
|
}
|
|
#endif
|