unicorn/qemu/target
Peter Maydell 730c99bcc2
Revert "target/arm: Implement HCR.VI and VF"
This reverts commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f.

The implementation of HCR.VI and VF in that commit is not
correct -- they do not track the overall "is there a pending
VIRQ or VFIQ" status, but whether there is a pending interrupt
due to "this mechanism", ie the hypervisor having set the VI/VF
bits. The overall pending state for VIRQ and VFIQ is effectively
the logical OR of the inbound lines from the GIC with the
VI and VF bits. Commit 8a0fc3a29fc231 would result in pending
VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR.

As a preliminary to implementing the HCR.VI/VF feature properly,
revert the broken one entirely.

Backports commit c624ea0fa7ffc9e2cc3e2b36c92b5c960954489f from qemu
2018-11-16 21:46:29 -05:00
..
arm Revert "target/arm: Implement HCR.VI and VF" 2018-11-16 21:46:29 -05:00
i386 target/i386: Clear RF on SYSCALL instruction 2018-11-11 08:41:09 -05:00
m68k m68k: Silence compiler warnings 2018-11-16 21:23:55 -05:00
mips target/mips: Amend MXU ASE overview note 2018-11-11 07:30:31 -05:00
sparc Sparc increase ttl number 2018-10-06 04:55:52 -04:00