Peter Maydell 730c99bcc2 Revert "target/arm: Implement HCR.VI and VF" ... This reverts commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f. The implementation of HCR.VI and VF in that commit is not correct -- they do not track the overall "is there a pending VIRQ or VFIQ" status, but whether there is a pending interrupt due to "this mechanism", ie the hypervisor having set the VI/VF bits. The overall pending state for VIRQ and VFIQ is effectively the logical OR of the inbound lines from the GIC with the VI and VF bits. Commit 8a0fc3a29fc231 would result in pending VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR. As a preliminary to implementing the HCR.VI/VF feature properly, revert the broken one entirely. Backports commit c624ea0fa7ffc9e2cc3e2b36c92b5c960954489f from qemu		2018-11-16 21:46:29 -05:00
..
arm-powerctl.c	target-arm: powerctl: Enable HVC when starting CPUs to EL2	2018-10-23 12:53:40 -04:00
arm-powerctl.h	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
arm_ldst.h	Fix Thumb-1 BE32 execution and disassembly.	2018-03-02 00:20:11 -05:00
cpu-qom.h	target/arm: Add "-cpu max" support	2018-03-12 10:11:49 -04:00
cpu.c	target/arm: Conditionalize some asserts on aarch32 support	2018-11-11 08:32:46 -05:00
cpu.h	arm: fix aa64_generate_debug_exceptions to work with EL2	2018-11-16 21:43:41 -05:00
cpu64.c	target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test	2018-11-10 08:34:32 -05:00
crypto_helper.c	target/arm/cpu and crypto_helper: Correct bad merge and adjust to qemu code style	2018-03-12 11:57:24 -04:00
helper-a64.c	target/arm: Check HAVE_CMPXCHG128 at translate time	2018-10-23 15:29:46 -04:00
helper-a64.h	target/arm: Implement FCMP for fp16	2018-05-15 22:24:39 -04:00
helper-sve.h	target/arm: Rewrite vector gather first-fault loads	2018-10-08 14:15:15 -04:00
helper.c	Revert "target/arm: Implement HCR.VI and VF"	2018-11-16 21:46:29 -05:00
helper.h	target/arm: Add v8M stack checks on ADD/SUB/MOV of SP	2018-10-08 14:15:15 -04:00
internals.h	target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode	2018-11-10 09:36:41 -05:00
iwmmxt_helper.c	target/arm: Untabify iwmmxt_helper.c	2018-08-25 04:33:44 -04:00
kvm-consts.h	arm: better stub version for MISMATCH_CHECK	2018-03-02 00:13:45 -05:00
Makefile.objs	target/arm: Implement SVE predicate test	2018-05-20 01:16:16 -04:00
neon_helper.c	target/*/cpu.h: remove softfloat.h	2018-03-08 09:58:47 -05:00
op_addsub.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
op_helper.c	target/arm: New utility function to extract EC from syndrome	2018-11-10 09:28:23 -05:00
psci.c	fix WFI/WFE length in syndrome register	2018-03-05 11:21:51 -05:00
sve.decode	target/arm: Implement SVE dot product (indexed)	2018-07-03 04:42:41 -04:00
sve_helper.c	sve_helper: Use the QEMU_FLATTEN macro instead of the compiler attribute directly	2018-10-23 13:05:02 -04:00
translate-a64.c	target/arm: Remove can't-happen if() from handle_vec_simd_shli()	2018-11-11 08:37:16 -05:00
translate-a64.h	arm: Take DisasContext as a parameter instead of TCGContext where applicable	2018-10-06 04:17:12 -04:00
translate-sve.c	decodetree: Remove insn argument from trans_* expanders	2018-11-11 08:27:01 -05:00
translate.c	target/arm: Reorg NEON VLD/VST single element to one lane	2018-11-10 11:24:37 -05:00
translate.h	target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE	2018-11-10 11:03:42 -05:00
unicorn.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
unicorn_aarch64.c	unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg	2018-09-03 07:47:40 +01:00
unicorn_arm.c	unicorn_arm: Allow for read/write of UC_ARM_REG_FPSCR	2018-09-03 21:03:55 +01:00
vec_helper.c	target/arm: Implement SVE dot product (indexed)	2018-07-03 04:42:41 -04:00