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target/arm: Remove can't-happen if() from handle_vec_simd_shli()

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In handle_vec_simd_shli() we have a check:

if (size > 3 && !is_q) {
    unallocated_encoding(s);
    return;
}

However this can never be true, because we calculate
int size = 32 - clz32(immh) - 1;
where immh is a 4 bit field which we know cannot be all-zeroes.
So the clz32() return must be in {28,29,30,31} and the resulting
size is in {0,1,2,3}, and "size > 3" is never true.

This unnecessary code confuses Coverity's analysis:
in CID 1396476 it thinks we might later index off the
end of an array because the condition implies that we
might have a size > 3.

Remove the code, and instead assert that the size is in [0..3],
since the decode that enforces that is somewhat distant from
this function.

Backports commit f6c98f91f56031141a47f86225fdc30f0f9f84fb from qemu
This commit is contained in:
Peter Maydell 2018-11-11 08:37:05 -05:00 committed by Lioncash
parent 834514c676
commit 5aa5ebbcc9
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 5 deletions
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8
qemu/target/arm/translate-a64.c
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@ -9629,12 +9629,10 @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
int immhb = immh << 3 | immb;
int shift = immhb - (8 << size);
if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s);
return;
}
/* Range of size is limited by decode: immh is a non-zero 4 bit field */
assert(size >= 0 && size <= 3);
if (size > 3 && !is_q) {
if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s);
return;
}