Richard Henderson 73ab332185 tcg/i386: Allow bmi2 shiftx to have non-matching operands ... Previously we could not have different constraints for different ISA levels, which prevented us from eliding the matching constraint for shifts. We do now have to make sure that the operands match for constant shifts. We can also handle some small left shifts via lea. Backports commit 6a5aed4bdc7078838a8098336588d56c9ce09d1d from qemu		2018-03-01 16:45:04 -05:00
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crypto
default-configs
docs
fpu
hw
include
qapi
qobject
qom
scripts
target-arm
target-i386	target-i386: Use clz and ctz opcodes	2018-03-01 16:17:42 -05:00
target-m68k
target-mips
target-sparc
tcg	tcg/i386: Allow bmi2 shiftx to have non-matching operands	2018-03-01 16:45:04 -05:00
util
aarch64.h	target-arm: Use clz opcode	2018-03-01 16:13:26 -05:00
aarch64eb.h
accel.c
arm.h
armeb.h
atomic_template.h
CODING_STYLE
configure
COPYING
COPYING.LIB
cpu-exec-common.c
cpu-exec.c
cpus.c
cputlb.c
exec.c
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glib_compat.c
HACKING
header_gen.py
ioport.c
LICENSE
m68k.h
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memory.c
memory_ldst.inc.c
memory_mapping.c
mips.h
mips64.h
mips64el.h
mipsel.h
powerpc.h
qapi-schema.json
qemu-timer.c
rules.mak
softmmu_template.h
sparc.h
sparc64.h
tcg-runtime.c
translate-all.c
translate-all.h
translate-common.c
unicorn_common.h
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vl.c
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x86_64.h