unicorn/qemu
Yongbok Kim 76ab1f17fb
target-mips: microMIPS32 R6 POOL16{A, C} instructions
microMIPS32 Release 6 POOL16A/ POOL16C instructions

Backports commit ed7ce6c0f9d4370826557ce33d652beb88ccb3e6 from qemu
2018-02-17 15:23:13 -05:00
..
default-configs
docs
fpu
hw qerror: Clean up QERR_ macros to expand into a single string 2018-02-17 15:23:09 -05:00
include qerror: Move #include out of qerror.h 2018-02-17 15:23:10 -05:00
qapi qerror: Clean up QERR_ macros to expand into a single string 2018-02-17 15:23:09 -05:00
qobject qerror: Finally unused, clean up 2018-02-17 15:23:10 -05:00
qom qerror: Clean up QERR_ macros to expand into a single string 2018-02-17 15:23:09 -05:00
scripts
target-arm target-arm: Add support for Cortex-R5 2018-02-17 15:23:08 -05:00
target-i386 qerror: Clean up QERR_ macros to expand into a single string 2018-02-17 15:23:09 -05:00
target-m68k m68k: fix usp processing on interrupt entry and exception exit 2018-02-17 15:23:09 -05:00
target-mips target-mips: microMIPS32 R6 POOL16{A, C} instructions 2018-02-17 15:23:13 -05:00
target-sparc
tcg
util
aarch64.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
aarch64eb.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
accel.c
arm.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
armeb.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
CODING_STYLE
configure
COPYING
COPYING.LIB
cpu-exec.c
cpus.c
cputlb.c
exec.c
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
ioport.c
LICENSE
m68k.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
Makefile
Makefile.objs
Makefile.target
memory.c
memory_mapping.c
mips.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
mips64.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
mips64el.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
mipsel.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
powerpc.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
qapi-schema.json
qemu-log.c
qemu-timer.c
rules.mak
softmmu_template.h
sparc.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
sparc64.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00
tcg-runtime.c
translate-all.c translate-all: fix watchpoints if retranslation not possible 2018-02-17 15:22:43 -05:00
translate-all.h
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h target-mips: Misaligned memory accesses for MSA 2018-02-13 13:27:31 -05:00