Kirill A. Shutemov eb489625b5 x86: implement la57 paging mode ... The new paging more is extension of IA32e mode with more additional page table level. It brings support of 57-bit vitrual address space (128PB) and 52-bit physical address space (4PB). The structure of new page table level is identical to pml4. The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]. CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level paging mode. Backports commit 6c7c3c21f95dd9af8a0691c0dd29b07247984122 from qemu		2018-03-01 11:02:07 -05:00
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arch_memory_mapping.c	x86: implement la57 paging mode	2018-03-01 11:02:07 -05:00
bpt_helper.c	target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns	2018-03-01 10:56:22 -05:00
cc_helper.c
cc_helper_template.h
cpu-qom.h
cpu.c	x86: implement la57 paging mode	2018-03-01 11:02:07 -05:00
cpu.h	x86: implement la57 paging mode	2018-03-01 11:02:07 -05:00
excp_helper.c
fpu_helper.c
helper.c	x86: implement la57 paging mode	2018-03-01 11:02:07 -05:00
helper.h	target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns	2018-03-01 10:56:22 -05:00
int_helper.c
Makefile.objs
mem_helper.c
misc_helper.c
mpx_helper.c
ops_sse.h
ops_sse_header.h
seg_helper.c
shift_helper_template.h
smm_helper.c
svm.h
svm_helper.c
TODO
topology.h
translate.c	target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns	2018-03-01 10:56:22 -05:00
unicorn.c
unicorn.h