unicorn/qemu/target
Peter Maydell 7861820e94
target/arm: Implement XPSR GE bits
In the M-profile architecture, if the CPU implements the DSP extension
then the XPSR has GE bits, in the same way as the A-profile CPSR. When
we added DSP extension support we forgot to add support for reading
and writing the GE bits, which are stored in env->GE. We did put in
the code to add XPSR_GE to the mask of bits to update in the v7m_msr
helper, but forgot it in v7m_mrs. We also must not allow the XPSR we
pull off the stack on exception return to set the nonexistent GE bits.
Correct these errors:
* read and write env->GE in xpsr_read() and xpsr_write()
* only set GE bits on exception return if DSP present
* read GE bits for MRS if DSP present

Backports commit f1e2598c46d480c9e21213a244bc514200762828 from qemu
2019-05-09 17:46:31 -04:00
..
arm target/arm: Implement XPSR GE bits 2019-05-09 17:46:31 -04:00
i386 target/i386: check CF_PARALLEL instead of parallel_cpus 2019-05-04 22:45:49 -04:00
m68k target/m68k: check CF_PARALLEL instead of parallel_cpus 2019-05-06 00:42:16 -04:00
mips tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
riscv decodetree: Add DisasContext argument to !function expanders 2019-05-09 17:40:45 -04:00
sparc target/sparc: check CF_PARALLEL instead of parallel_cpus 2019-05-06 00:43:21 -04:00