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unicorn/qemu/target/riscv/insn_trans
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Alistair Francis 4972437f93 target/riscv: Allow generating hlv/hlvx/hsv instructions 
Backports 8c5362acb573b8b1913238a5ddefdeef12f513a8
2021-03-08 13:13:32 -05:00
..
trans_privileged.inc.c target/riscv: Move the hfence instructions to the rvh decode 2021-02-25 11:59:49 -05:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvd.inc.c target/riscv: check before allocating TCG temps 2021-03-08 12:41:19 -05:00
trans_rvf.inc.c target/riscv: check before allocating TCG temps 2021-03-08 12:41:19 -05:00
trans_rvh.inc.c target/riscv: Allow generating hlv/hlvx/hsv instructions 2021-03-08 13:13:32 -05:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00
trans_rvv.inc.c target/riscv: fix vector index load/store constraints 2021-03-08 12:16:45 -05:00