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unicorn/qemu/target
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Richard Henderson 8360c1fa3b
target/riscv: Merge argument decode for RVC shifti 
Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti. This can be handled with !function.

Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu
2019-05-28 18:52:50 -04:00
..
arm target/arm: Fix vector operation segfault 2019-05-24 18:02:32 -04:00
i386 target/i386: Implement CPUID_EXT_RDRAND 2019-05-23 15:12:50 -04:00
m68k target/m68k: Optimize rotate_x() using extract_i32() 2019-05-17 12:07:07 -04:00
mips tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00
riscv target/riscv: Merge argument decode for RVC shifti 2019-05-28 18:52:50 -04:00
sparc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00