Richard Henderson 8360c1fa3b target/riscv: Merge argument decode for RVC shifti ... Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu		2019-05-28 18:52:50 -04:00
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trans_privileged.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvc.inc.c	target/riscv: Merge argument decode for RVC shifti	2019-05-28 18:52:50 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00