Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
..
arm.h	Add ARM MSP, PSP and CONTROL register access (#1071)	2019-03-08 02:24:49 -05:00
arm64.h	aarch64: Add FPCR and FPSR registers	2018-01-16 17:37:47 +00:00
m68k.h	LGPL2 for all header files under include/unicorn/	2017-12-16 10:08:42 +08:00
mips.h	LGPL2 for all header files under include/unicorn/	2017-12-16 10:08:42 +08:00
platform.h	LGPL2 for all header files under include/unicorn/	2017-12-16 10:08:42 +08:00
riscv.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
sparc.h	LGPL2 for all header files under include/unicorn/	2017-12-16 10:08:42 +08:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
x86.h	target/i386: Added MXCSR register, fixed writing to FPUCW. (#1059)	2019-02-28 16:31:22 -05:00