Leon Alrae 8743ec8b6d target-mips: add MTHC0 and MFHC0 instructions ... Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Backports commit 5204ea79ea739b557f47fc4db96c94edcb33a5d6 from qemu		2018-02-13 14:03:59 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
cpu.h	target-mips: add MTHC0 and MFHC0 instructions	2018-02-13 14:03:59 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: remove excp_names[] from linux-user as it is unused	2018-02-11 17:05:40 -05:00
helper.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	target-mips: add CP0.PageGrain.ELPA support	2018-02-13 13:55:53 -05:00
msa_helper.c	target-mips: add missing MSACSR and restore fp_status and hflags	2018-02-12 16:12:17 -05:00
op_helper.c	target-mips: add CP0.PageGrain.ELPA support	2018-02-13 13:55:53 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: add MTHC0 and MFHC0 instructions	2018-02-13 14:03:59 -05:00
translate_init.c	target-mips: add Config5.FRE support allowing Status.FR=0 emulation	2018-02-13 13:05:22 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00