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Peter Maydell 89baa5cffa
target/arm: Decode FP instructions for M profile 
Correct the decode of the M-profile "coprocessor and
floating-point instructions" space:
* op0 == 0b11 is always unallocated
* if the CPU has an FPU then all insns with op1 == 0b101
are floating point and go to disas_vfp_insn()

For the moment we leave VLLDM and VLSTM as NOPs; in
a later commit we will fill in the proper implementation
for the case where an FPU is present.

Backports commit 8859ba3c9625e7ceb5599f457a344bcd7c5e112b from qemu
2019-04-30 10:19:45 -04:00
..
arm target/arm: Decode FP instructions for M profile 2019-04-30 10:19:45 -04:00
i386 tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
m68k tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
mips tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
riscv tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
sparc tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00