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unicorn/qemu/target
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Alex Richardson 8e4e0a6993 target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR 
The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).

Backports 529577457cbba9e429af629c46204f63e50fa832
2021-03-08 15:16:50 -05:00
..
arm qemu/atomic.h: rename atomic_ to qatomic_ 2021-03-08 14:34:35 -05:00
i386 qemu/atomic.h: rename atomic_ to qatomic_ 2021-03-08 14:34:35 -05:00
m68k m68k: Fix build 2021-03-05 08:29:53 -05:00
mips mips: Fix build 2021-03-05 08:51:51 -05:00
riscv target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR 2021-03-08 15:16:50 -05:00
sparc sparc: Fix build 2021-03-05 08:54:43 -05:00