LIU Zhiwei 8fe29be764 target/riscv: Clean up fmv.w.x ... Use tcg_gen_extu_tl_i64 to avoid the ifdef. Backports 6e0229e63868b8b5bfcc54959cea227ed19f7bd3		2021-03-08 12:39:38 -05:00
..
trans_privileged.inc.c	target/riscv: Move the hfence instructions to the rvh decode	2021-02-25 11:59:49 -05:00
trans_rva.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
trans_rvd.inc.c	target/riscv: fsd/fsw doesn't dirty FP state	2020-03-21 12:20:52 -04:00
trans_rvf.inc.c	target/riscv: Clean up fmv.w.x	2021-03-08 12:39:38 -05:00
trans_rvh.inc.c	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
trans_rvi.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00
trans_rvv.inc.c	target/riscv: fix vector index load/store constraints	2021-03-08 12:16:45 -05:00