unicorn/qemu/target/arm
Peter Maydell 96f86f472a
target/arm: Pull Thumb insn word loads up to top level
Refactor the Thumb decode to do the loads of the instruction words at
the top level rather than only loading the second half of a 32-bit
Thumb insn in the middle of the decode.

This is simple apart from the awkward case of Thumb1, where the
BL/BLX prefix and suffix instructions live in what in Thumb2 is the
32-bit insn space. To handle these we decode enough to identify
whether we're looking at a prefix/suffix that we handle as a 16 bit
insn, or a prefix that we're going to merge with the following suffix
to consider as a 32 bit insn. The translation of the 16 bit cases
then moves from disas_thumb2_insn() to disas_thumb_insn().

The refactoring has the benefit that we don't need to pass the
CPUARMState* down into the decoder code any more, but the major
reason for doing this is that some Thumb instructions must be always
unconditional regardless of the IT state bits, so we need to know the
whole insn before we emit the "skip this insn if the IT bits and cond
state tell us to" code. (The always unconditional insns are BKPT,
HLT and SG; the last of these is 32 bits.)

Backports commit 296e5a0a6c393553079a641c50521ae33ff89324 from qemu
2018-03-05 03:43:38 -05:00
..
arm-powerctl.c ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2018-03-02 00:20:11 -05:00
cpu-qom.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
cpu.c nvic: Implement Security Attribution Unit registers 2018-03-05 01:55:11 -05:00
cpu.h target/arm: Factor out "get mmuidx for specified security state" 2018-03-05 02:00:23 -05:00
cpu64.c target-arm: Enable EL2 feature bit on A53 and A57 2018-03-01 23:36:44 -05:00
crypto_helper.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
helper-a64.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
helper-a64.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
helper.c target/arm: Implement secure function return 2018-03-05 03:33:42 -05:00
helper.h target/arm: Implement BLXNS 2018-03-05 03:31:59 -05:00
internals.h target/arm: Implement secure function return 2018-03-05 03:33:42 -05:00
iwmmxt_helper.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
Makefile.objs ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
neon_helper.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c arm: Fix SMC reporting to EL2 when QEMU provides PSCI 2018-03-05 01:19:22 -05:00
psci.c target/arm/psci.c: If EL2 implemented, start CPUs in EL2 2018-03-01 23:34:57 -05:00
translate-a64.c tcg: remove addr argument from lookup_tb_ptr 2018-03-05 02:16:34 -05:00
translate.c target/arm: Pull Thumb insn word loads up to top level 2018-03-05 03:43:38 -05:00
translate.h target/arm: Implement BXNS, and banked stack pointers 2018-03-04 21:21:23 -05:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_arm.c Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00