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https://github.com/yuzu-emu/unicorn.git
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7f1bc28513
Add definition use_mips32r6_instructions to the MIPS TCG backend which is constant 1 when built for MIPS release 6. This will be used to decide between pre-R6 and R6 instruction encodings. Backports commit ce14bd4d469f3a14f6cbfceb6360aee066a60d72 from qemu
146 lines
4.5 KiB
C
146 lines
4.5 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
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* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
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* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef TCG_TARGET_MIPS
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#define TCG_TARGET_MIPS 1
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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#define TCG_TARGET_NB_REGS 32
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typedef enum {
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TCG_REG_ZERO = 0,
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TCG_REG_AT,
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TCG_REG_V0,
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TCG_REG_V1,
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TCG_REG_A0,
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TCG_REG_A1,
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TCG_REG_A2,
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TCG_REG_A3,
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TCG_REG_T0,
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TCG_REG_T1,
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TCG_REG_T2,
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TCG_REG_T3,
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TCG_REG_T4,
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TCG_REG_T5,
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TCG_REG_T6,
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TCG_REG_T7,
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TCG_REG_S0,
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TCG_REG_S1,
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TCG_REG_S2,
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TCG_REG_S3,
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TCG_REG_S4,
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TCG_REG_S5,
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TCG_REG_S6,
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TCG_REG_S7,
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TCG_REG_T8,
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TCG_REG_T9,
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TCG_REG_K0,
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TCG_REG_K1,
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TCG_REG_GP,
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TCG_REG_SP,
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TCG_REG_S8,
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TCG_REG_RA,
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TCG_REG_CALL_STACK = TCG_REG_SP,
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TCG_AREG0 = TCG_REG_S0,
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} TCGReg;
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_STACK_OFFSET 16
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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/* MOVN/MOVZ instructions detection */
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#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
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defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
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defined(_MIPS_ARCH_MIPS4)
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#define use_movnz_instructions 1
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#else
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extern bool use_movnz_instructions;
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#endif
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/* MIPS32 instruction set detection */
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#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
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#define use_mips32_instructions 1
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#else
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extern bool use_mips32_instructions;
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#endif
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/* MIPS32R2 instruction set detection */
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#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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#define use_mips32r2_instructions 1
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#else
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extern bool use_mips32r2_instructions;
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#endif
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/* MIPS32R6 instruction set detection */
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#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
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#define use_mips32r6_instructions 1
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#else
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#define use_mips32r6_instructions 0
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#endif
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 1
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#define TCG_TARGET_HAS_mulsh_i32 1
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/* optional instructions detected at runtime */
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#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
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#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_bswap32_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
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#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
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#ifdef __OpenBSD__
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#include <machine/sysarch.h>
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#else
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#include <sys/cachectl.h>
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#endif
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static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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cacheflush ((void *)start, stop-start, ICACHE);
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}
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#endif
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