unicorn

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Commit graph

Author	SHA1	Message	Date
James Hogan	7f1bc28513	tcg/mips: Add use_mips32r6_instructions definition Add definition use_mips32r6_instructions to the MIPS TCG backend which is constant 1 when built for MIPS release 6. This will be used to decide between pre-R6 and R6 instruction encodings. Backports commit ce14bd4d469f3a14f6cbfceb6360aee066a60d72 from qemu	2018-02-17 15:24:04 -05:00
Paolo Bonzini	b34c233c2f	tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which sometimes, as in the case of Aarch64, extend to instructions that shift the immediate). Backports commit 006f8638c62bca2b0caf609485f47fa5e14d8a3c from qemu	2018-02-13 08:28:29 -05:00
Nguyen Anh Quynh	344d016104	import	2015-08-21 15:04:50 +08:00

Author

SHA1

Message

Date

James Hogan

7f1bc28513

tcg/mips: Add use_mips32r6_instructions definition

Add definition use_mips32r6_instructions to the MIPS TCG backend which
is constant 1 when built for MIPS release 6. This will be used to decide
between pre-R6 and R6 instruction encodings.

Backports commit ce14bd4d469f3a14f6cbfceb6360aee066a60d72 from qemu

2018-02-17 15:24:04 -05:00

Paolo Bonzini

b34c233c2f

tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS

This will be used to size the TLB when more than 8 MMU modes are
used by the target. Limitations come from the limited size of
the immediate fields (which sometimes, as in the case of Aarch64,
extend to instructions that shift the immediate).

Backports commit 006f8638c62bca2b0caf609485f47fa5e14d8a3c from qemu

2018-02-13 08:28:29 -05:00

Nguyen Anh Quynh

344d016104

import

2015-08-21 15:04:50 +08:00

3 commits