Commit graph

2352 commits

Author SHA1 Message Date
James Hogan 9dac598855
tcg/mips: Support r6 JR encoding
MIPSr6 encodes JR as JALR with zero as the link register, and the pre-r6
JR encoding is removed. Update TCG to use the new encoding when built
for r6.

We still use the old encoding for pre-r6, so as not to confuse return
prediction stack hardware which may detect only particular encodings of
the return instruction.

Backports commit 6e0d096989be52c2b945fc83a9bd15d887bbdb47 from qemu
2018-02-17 15:24:04 -05:00
James Hogan 7f1bc28513
tcg/mips: Add use_mips32r6_instructions definition
Add definition use_mips32r6_instructions to the MIPS TCG backend which
is constant 1 when built for MIPS release 6. This will be used to decide
between pre-R6 and R6 instruction encodings.

Backports commit ce14bd4d469f3a14f6cbfceb6360aee066a60d72 from qemu
2018-02-17 15:24:04 -05:00
James Hogan 9d3a2feea0
tcg-opc.h: Simplify insn_start def
We already have a TLADDR_ARGS definition, so rearrange the order
slightly and use it in the definition of insn_start, instead of
having an #ifdef.

Backports commit c0e40dbdcc291c85faa289a53be60b7b1b7c7598 from qemu
2018-02-17 15:24:03 -05:00
Richard Henderson d167379211
tcg/ppc: Prefer mask over andi.
Prefer the instruction that isn't required to modify cr0.

Backports commit 1e1df962e325e18a5188c4814cd1a10215a48f79 from qemu
2018-02-17 15:24:03 -05:00
Richard Henderson 3c3dee3747
tcg/ppc: Revise goto_tb implementation
Restrict the size of code_gen_buffer to 2GB on ppc64, which
lets us assert that everything is reachable with addis+addi
from tb_ret_addr. This lets us use a max of 4 insns for goto_tb
instead of 7.

Emit the indirect branch portion of goto_tb up front, which
means we only have to update two insns to update any link.
With a 64-bit store, we can update the link atomically, which
may be required in future.

Backports commit 5bfd75a35c11dd3aa61c73d0d2cd88137c31519c from qemu
2018-02-17 15:24:03 -05:00
Richard Henderson 13ad21a21f
tcg/ppc: Adjust exit_tb for change in prologue placement
Changing the prologue to the beginning of the code_gen_buffer
changes the direction of the "return" branch. Need to change
the logic to match.

Backports commit 70f897bdc4ce4101ec008317d43090f532bfb07d from qemu
2018-02-17 15:24:03 -05:00
Michael S. Tsirkin 722c58affb
exec: factor out duplicate mmap code
Anonymous and file-backed RAM allocation are now almost exactly the same.

Reduce code duplication by moving RAM mmap code out of oslib-posix.c and
exec.c.

Backports commit 794e8f301a17953efa78ab7538019ec43c59e82a from qemu
2018-02-17 15:24:03 -05:00
Sergey Fedorov e4e0c75f0f
target-arm: Fix CPU breakpoint handling
A QEMU breakpoint match is not definitely an architectural breakpoint
match. If an exception is generated unconditionally during translation,
it is hardly possible to ignore it in the debug exception handler.

Generate a call to a helper to check CPU breakpoints and raise an
exception only if any breakpoint matches architecturally.

Backports commit 5d98bf8f38c17a348ab6e8af196088cd4953acd0 from qemu
2018-02-17 15:24:02 -05:00
Sergey Fedorov 4706e10887
target-arm: Fix GDB breakpoint handling
GDB breakpoints have higher priority so they have to be checked first.
Should GDB breakpoint match, just return from the debug exception
handler.

Backports commit e63a2d4d9ed73e33a0b7483085808048be8bbcb1 from qemu
2018-02-17 15:24:02 -05:00
Sergey Fedorov cb04e919ab
target-arm: implement arm_debug_target_el()
Implement debug exception routing according to ARM ARM D2.3.1 Pseudocode
description of routing debug exceptions.

Backports commit 81669b8b81eb450d7b89ee5fdd57bdb73d87022d from qemu
2018-02-17 15:24:02 -05:00
Sergey Fedorov 9b5cd0cec1
target-arm: Add MDCR_EL2
Add the MDCR_EL2 register. We don't implement any of
the debug-related traps this register controls yet, so
currently it simply reads back as written.

Backports commit 14cc7b54372995a6ba72c7719372e4f710fc9b5a from qemu
2018-02-17 15:24:02 -05:00
Davorin Mista cc2e6fc4e4
target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs
Added oslar_write function to OSLAR_EL1 sysreg, using a status variable
in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked
to the newly added read-only OSLSR_EL1 register.

Linux reads from this register during its suspend/resume procedure.

Backports commit 1424ca8d4320427c3e93722b65e19077969808a2 from qemu
2018-02-17 15:24:01 -05:00
Sergey Sorokin 1152631b4b
target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL
It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
This patch fixes several attempts to do so.

Backports commit 2cde031f5a34996bab32571a26b1a6bcf3e5b5d9 from qemu
2018-02-17 15:24:01 -05:00
Sergey Sorokin 04992f0fb3
target-arm: Break the TB after ISB to execute self-modified code correctly
If any store instruction writes the code inside the same TB
after this store insn, the execution of the TB must be stopped
to execute new code correctly.
As described in ARMv8 manual D3.4.6 self-modifying code must do an
IC invalidation to be valid, and an ISB after it. So it's enough to end
the TB after ISB instruction on the code translation.
Also this TB break is necessary to take any pending interrupts immediately
after an ISB (as required by ARMv8 ARM D1.14.4).

Backports commit 6df99dec9e81838423d723996e96236693fa31fe from qemu
2018-02-17 15:24:01 -05:00
Stefan Weil d1bba24d86
target-arm: Add missing 'static' attribute
Backports commit 82c39f6a8898b028515eddcdbc4ae50959d0af5d from qemu
2018-02-17 15:24:01 -05:00
Richard Henderson a276496ebc
tcg: Adjust CODE_GEN_AVG_BLOCK_SIZE
At present, the "average" guestimate of TB size is way too small, leading
to many unused entries in the pre-allocated TB array. For a guest with 1GB
ram, we're currently allocating 256MB for the array.

Survey arm, alpha, aarch64, ppc, sparc, i686, x86_64 guests running on
x86_64 and ppc64 hosts and select a new average. The size of the array
drops to 81MB with no more flushing than before.

Backports commit 126d89e8cdfa3be15d51f76906eaccbcd0023f98 from qemu
2018-02-17 15:24:01 -05:00
Richard Henderson bdf667fd4e
tcg: Check for overflow via highwater mark
We currently pre-compute an worst case code size for any TB, which
works out to be 122kB. Since the average TB size is near 1kB, this
wastes quite a lot of storage.

Instead, check for overflow in between generating code for each opcode.
The overhead of the check isn't measurable and wastage is minimized.

Backports commit b125f9dc7bd68cd4c57189db4da83b0620b28a72 from qemu
2018-02-17 15:24:00 -05:00
Richard Henderson 71221baf40
tcg: Allocate a guard page after code_gen_buffer
This will catch any overflow of the buffer.

Add a native win32 alternative for alloc_code_gen_buffer;
remove the malloc alternative.

Backports commit f293709c6af7a65a9bcec09cdba7a60183657a3e from qemu
2018-02-17 15:24:00 -05:00
Richard Henderson 19a3c7e03f
tcg: Emit prologue to the beginning of code_gen_buffer
By putting the prologue at the end, we risk overwriting the
prologue should our estimate of maximum TB size. Given the
two different placements of the call to tcg_prologue_init,
move the high water mark computation into tcg_prologue_init.

Backports commit 8163b74938d8b7d12e70597c4553dd0dc49443d5 from qemu
2018-02-17 15:24:00 -05:00
Richard Henderson 532877a366
tcg: Remove tcg_gen_code_search_pc
It's no longer used, so tidy up everything reached by it.

Backports commit 04fe64000162c45d8974da9ca4d266f8d0e67eb7 from qemu
2018-02-17 15:24:00 -05:00
Lioncash f0f8d5764a
target-m68k: Silence unused variable warning 2018-02-17 15:24:00 -05:00
Richard Henderson a5ac288135
tcg: Remove gen_intermediate_code_pc
It is no longer used, so tidy up everything reached by it.
This includes the gen_opc_* arrays, the search_pc parameter
and the inline gen_intermediate_code_internal functions.

Backports commit 4e5e1215156662b2b153255c49d4640d82c5568b from qemu
2018-02-17 15:23:59 -05:00
Richard Henderson 66de6cc37c
tcg: Save insn data and use it in cpu_restore_state_from_tb
We can now restore state without retranslation.

Backports commit fca8a500d519a56abeaedf8073167a61d3c6b9c4 from qemu
2018-02-17 15:23:59 -05:00
Richard Henderson a7cf761caf
tcg: Merge cpu_gen_code into tb_gen_code
As it's only caller, this tidies things a bit.

Backports commit fec88f64bda27846add83e924c8f4def9d94e068 from qemu
2018-02-17 15:23:59 -05:00
Paolo Bonzini 268275f04b
translate: check cflags instead of use_icount global
Backports applicable parts of commit bd79255d2571a3c68820117caf94ea9afe1d527e
2018-02-17 15:23:59 -05:00
Paolo Bonzini cab4c979f0
cpu-exec: add a new CF_USE_ICOUNT cflag
Backports commit 0266359e57987d6be53fbcb885f2dd39c1dae940 from qemu
2018-02-17 15:23:58 -05:00
Pavel Dovgalyuk ac46898b3c
cpu-exec: invalidate nocache translation if they are interrupted
In this case, QEMU might longjmp out of cpu-exec.c and miss the final
cleanup in cpu_exec_nocache.  Do this manually through a new compile
flag.

Backports commit d8a499f17ee5f05407874f29f69f0e3e3198a853 from qemu
2018-02-17 15:23:58 -05:00
Richard Henderson 1cbd175736
tcg: Pass data argument to restore_state_to_opc
The gen_opc_* arrays are already redundant with the data stored in
the insn_start arguments. Transition restore_state_to_opc to use
data from the latter.

Backports commit bad729e272387de7dbfa3ec4319036552fc6c107 from qemu
2018-02-17 15:23:58 -05:00
Lioncash b115c5509d
tcg: Add TCG_MAX_INSNS
Adjust all translators to respect it.

Backports commit 190ce7fbc79fd0883a6170d7f30da59d366e6830 from qemu
2018-02-17 15:23:58 -05:00
Lioncash ecfc306668
Update MSVC projects 2018-02-17 15:23:57 -05:00
Lioncash f8d54a8f3c
Drop unused crypto source files 2018-02-17 15:23:57 -05:00
Richard Henderson 5637099383
target-*: Drop cpu_gen_code define
This symbol no longer exists.

Backports commit dc03246cc377268db63abc8c5663ef571aec2eea from qemu
2018-02-17 15:23:57 -05:00
Richard Henderson 25e0621757
target-sparc: Add npc state to insn_start
Backports commit a3d5ad761cafc669e25f4185e63d8d758a989135 from qemu
2018-02-17 15:23:57 -05:00
Richard Henderson 2c1ae7a408
target-sparc: Remove gen_opc_jump_pc
Since jump_pc[1] is always npc + 4, we can infer after incrementing
that jump_pc[1] == pc + 4. Because of that, we can encode the branch
destination into a single word, and store that in npc.

Backports commit 6c42444f9a53b6af39d46008cb9f650b11e96cb9 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson b709d15b13
target-sparc: Split out gen_branch_n
Unify three copies of this code from different
branch types. Fix the case when npc == DYNAMIC_PC,
i.e. a branch within a delay slot.

Backports commit 2bf2e019ed0a6349220620240c0ba807846793b9 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson ee918c940c
target-sparc: Tidy gen_branch_a interface
We always pass pc2 == dc->npc and r_cond == cpu_cond,
and always set is_br afterward. Infer all of that.

Backports commit bfa31b765798139804ce9e5e35c7e142d233df31 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson f05c35c49c
target-i386: Add cc_op state to insn_start
Backports commit 2066d09516ba34d0d180fdea451436d9babb3308 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson 500e116581
target-mips: Add delayed branch state to insn_start
Backports commit c20d594e45bc8c4b21be1a7637cba0f279f72879 from qemu
2018-02-17 15:23:56 -05:00
Paolo Bonzini 96e0535c76
target-i386: add ABM to Haswell* and Broadwell* CPU models
ABM is only implemented as a single instruction set by AMD; all AMD
processors support both instructions or neither. Intel considers POPCNT
as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
ABM flag to indicate support for both POPCNT and LZCNT. It has to be
added to Haswell and Broadwell because Haswell, by adding LZCNT, has
completed the ABM.

Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
machine types) on an Haswell-EP machine.

Backports commit becb66673ec30cb604926d247ab9449a60ad8b11 from qemu
2018-02-17 15:23:55 -05:00
Bill Paul 5b14f0ed52
Correctly re-init EFER state during INIT IPI
When doing a re-initialization of a CPU core, the default state is to _not_
have 64-bit long mode enabled. This means the LME (long mode enable) and LMA
(long mode active) bits in the EFER model-specific register should be cleared.

However, the EFER state is part of the CPU environment which is
preserved by do_cpu_init(), so if EFER.LME and EFER.LMA were set at the
time an INIT IPI was received, they will remain set after the init completes.

This is contrary to what the Intel architecture manual describes and what
happens on real hardware, and it leaves the CPU in a weird state that the
guest can't clear.

To fix this, the 'efer' member of the CPUX86State structure has been moved
to an area outside the region preserved by do_cpu_init(), so that it can
be properly re-initialized by x86_cpu_reset().

Backports commit 2188cc52cb363433751f72b991d8fb05fc60e39d from qemu
2018-02-17 15:23:55 -05:00
Lioncash da8e73b887
qom/cpu: Add throttle_thread_scheduled member
Extracts the member out of commit 2adcc85d407c1ab985f5abed808c78dbb84f4773
2018-02-17 15:23:55 -05:00
Peter Crosthwaite 1faea35feb
i386: Rename ELF_MACHINE to be x86 specific
Rename ELF_MACHINE to be I386 specific. This is used as-is by the
multiboot loader.

Linux-user previously used this definition but will not anymore,
falling back to the default bahaviour of using ELF_ARCH as ELF_MACHINE.

This removes another architecture specific definition from the global
namespace.

Backports commit a5e8788f89312f19f54dba0454ee5bf7209b4cd7 from qemu
2018-02-17 15:23:55 -05:00
Peter Crosthwaite 95bcb2f144
mips: Remove ELF_MACHINE from cpu.h
The only generic code relying on this is linux-user, but linux users'
default behaviour of defaulting ELF_MACHINE to ELF_ARCH will handle
this.

The bootloaders can just pass EM_MIPS directly, as that is
architecture specific code.

This removes another architecture specific definition from the global
namespace.

Backports commit 04ce380e9e3fad1dbf4e86ebdf9315573a06b30e from qemu
2018-02-17 15:23:55 -05:00
Peter Crosthwaite 23dc795806
sparc: Remove ELF_MACHINE from cpu.h
The bootloaders can just pass EM_SPARC or EM_SPARCV9 directly, as
they are architecture specific code (to one or the other).

This removes another architecture specific definition from the global
namespace.

Backports commit 77452383e0c45704e2339b58eac29a3730bc18b1 from qemu
2018-02-17 15:23:55 -05:00
Peter Crosthwaite b848c7a51f
m68k: Remove ELF_MACHINE from cpu.h
The only generic code relying on this is linux-user, but linux users'
default behaviour of defaulting ELF_MACHINE to ELF_ARCH will handle
this.

The machine model bootloaders can just pass EM_68K directly, as that
is architecture specific code.

This removes another architecture specific definition from the global
namespace.

Backports commit 45e6b8b61a7bbb71d1fa6c4193b47ba3a1f9f033 from qemu
2018-02-17 15:23:54 -05:00
Peter Crosthwaite 9f8b8ba793
arm: Remove ELF_MACHINE from cpu.h
The only generic code relying on this is linux-user. Linux user
already has a lot of #ifdef TARGET_ customisation so instead, define
ELF_ARCH as either EM_ARM or EM_AARCH64 appropriately.

The armv7m bootloader can just pass EM_ARM directly, as that
is architecture specific code. Note that arm_boot already has its own
logic selecting an arm specific elf machine so this makes V7M more
consistent with arm_boot.

This removes another architecture specific definition from the global
namespace.

Backports commit b597c3f7da17fcb37d394a16a6c0ef0a02846177 from qemu
2018-02-17 15:23:54 -05:00
Pavel Butsykin 96f8d6325a
apic_internal.h: fix formatting and drop unused consts
Fix formatting of local apic definitions and drop unused constant
APIC_INPUT_POLARITY, APIC_SEND_PENDING. Magic numbers in shifts are
replaced with constants defined just above.

Backports commit b6cfc3c2ac5a1025d8fe7d74421a73ec495408f9 from qemu
2018-02-17 15:23:54 -05:00
Pavel Butsykin 79559c82aa
apic_internal.h: rename ESR_ILLEGAL_ADDRESS to APIC_ESR_ILLEGAL_ADDRESS
Added prefix APIC_ for determining the constant of a particular subsystem,
improve the overall readability and match other constant names.

Backports commit a22bf99c5852f369dc620be2c3c93535a5b69a58 from qemu
2018-02-17 15:23:54 -05:00
Pavel Butsykin fcd3e3e449
apic_internal.h: added more constants
These constants are needed for optimal access to
bit fields local apic registers without magic numbers.

Backports commit 6519d187e301c5a14a8c9b32fb93027b04a4336d from qemu
2018-02-17 15:23:54 -05:00
Aurelien Jarno b5f5e2dbc2
tcg/mips: pass oi to tcg_out_tlb_load
Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and
tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly
pass oi to the tcg_out_tlb_load function and compute mem_index and
s_bits there.

Backports commit 81dfaf1a8f7f95259801da9732472f879023ef77 from qemu
2018-02-17 15:23:54 -05:00