Yongbok Kim a35a59bda6 target/mips: Add CP0 PWCtl register ... Add PWCtl register (CP0 Register 5, Select 6). The PWCtl register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: PWEn (31) - Hardware Page Table walker enable PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only) XK (28) - If 1, walker handles xkseg (MIPS64 only) XS (27) - If 1, walker handles xsseg (MIPS64 only) XU (26) - If 1, walker handles xuseg (MIPS64 only) DPH (7) - Dual Page format of Huge Page support HugePg (6) - Huge Page PTE supported in Directory levels PSn (5..0) - Bit position of PTEvld in Huge Page PTE Backports commit 103be64c26c166f12b3e1308edadef3443723ff1 from qemu		2018-10-23 14:23:04 -04:00
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arm	sve_helper: Use the QEMU_FLATTEN macro instead of the compiler attribute directly	2018-10-23 13:05:02 -04:00
i386	Initializes i386 prefix value	2018-10-06 04:57:06 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Add CP0 PWCtl register	2018-10-23 14:23:04 -04:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00