Yongbok Kim a5194f6dfc target/mips: Add CP0 PWSize register ... Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: BDW (37..32) Base Directory index width (MIPS64 only) GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Backports commit 20b28ebc49945583d7191b57755cfd92433de9ff from qemu		2018-10-23 14:08:55 -04:00
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arm	sve_helper: Use the QEMU_FLATTEN macro instead of the compiler attribute directly	2018-10-23 13:05:02 -04:00
i386	Initializes i386 prefix value	2018-10-06 04:57:06 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Add CP0 PWSize register	2018-10-23 14:08:55 -04:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00