unicorn/qemu/target-mips
Yongbok Kim acede6f50c
target-mips: raise RI exceptions when FIR.PS = 0
64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.

Backports commit e29c962804c4dd3fabd44e703aa87eec555ed910 from qemu
2018-02-17 15:23:11 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c Fix for MIPS issue. (#733) 2017-01-23 12:39:34 +08:00
cpu.h target-mips: add MTHC0 and MFHC0 instructions 2018-02-13 14:03:59 -05:00
dsp_helper.c Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
helper.c target-mips: remove excp_names[] from linux-user as it is unused 2018-02-11 17:05:40 -05:00
helper.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
lmi_helper.c import 2015-08-21 15:04:50 +08:00
Makefile.objs import 2015-08-21 15:04:50 +08:00
mips-defs.h target-mips: add CP0.PageGrain.ELPA support 2018-02-13 13:55:53 -05:00
msa_helper.c target-mips: add missing MSACSR and restore fp_status and hflags 2018-02-12 16:12:17 -05:00
op_helper.c target-mips: add CP0.PageGrain.ELPA support 2018-02-13 13:55:53 -05:00
TODO import 2015-08-21 15:04:50 +08:00
translate.c target-mips: raise RI exceptions when FIR.PS = 0 2018-02-17 15:23:11 -05:00
translate_init.c target-mips: enable XPA and LPA features 2018-02-13 14:14:59 -05:00
unicorn.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
unicorn.h armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00