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unicorn/qemu/target/arm
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Stefan Hajnoczi 320b59ddb9 qemu/atomic.h: rename atomic_ to qatomic_ 
clang's C11 atomic_fetch_*() functions only take a C11 atomic type
pointer argument. QEMU uses direct types (int, etc) and this causes a
compiler error when a QEMU code calls these functions in a source file
that also included <stdatomic.h> via a system header file:

$ CC=clang CXX=clang++ ./configure ... && make
../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid)

Avoid using atomic_*() names in QEMU's atomic.h since that namespace is
used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h
and <stdatomic.h> can co-exist. I checked /usr/include on my machine and
searched GitHub for existing "qatomic_" users but there seem to be none.

This patch was generated using:

$ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \
sort -u >/tmp/changed_identifiers
$ for identifier in $(</tmp/changed_identifiers); do
sed -i "s%\<$identifier\>%q$identifier%g" \
$(git grep -I -l "\<$identifier\>")
done

I manually fixed line-wrap issues and misaligned rST tables.

Backports d73415a315471ac0b127ed3fad45c8ec5d711de1
2021-03-08 14:34:35 -05:00
..
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
arm-powerctl.c arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on() 2020-01-07 18:10:29 -05:00
arm-powerctl.h ARM: Factor out ARM on/off PSCI control functions 2018-03-01 23:31:47 -05:00
arm_ldst.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
cpu-param.h target/arm: Don't use a TLB for ARMMMUIdx_Stage2 2020-05-07 08:40:06 -04:00
cpu-qom.h arm: Fix typo in AARCH64_CPU_GET_CLASS definition 2021-03-01 18:03:29 -05:00
cpu.c target/arm/cpu: Update coding style to make checkpatch.pl happy 2021-03-08 11:35:28 -05:00
cpu.h target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe 2021-03-08 11:23:50 -05:00
cpu64.c target/arm: Enable FEAT_SSBS for max AARCH64 CPU 2021-03-08 11:26:20 -05:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
debug_helper.c target/arm: Stop assuming DBGDIDR always exists 2020-03-21 18:26:24 -04:00
helper-a64.c target/arm: Speed up aarch64 TBL/TBX 2021-03-08 11:31:24 -05:00
helper-a64.h target/arm: Speed up aarch64 TBL/TBX 2021-03-08 11:31:24 -05:00
helper-sve.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
helper.c target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks 2021-03-08 11:34:03 -05:00
helper.h target/arm: Fix neon VTBL/VTBX for len > 1 2021-03-02 13:23:13 -05:00
internals.h target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe 2021-03-08 11:23:50 -05:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
kvm-consts.h arm: better stub version for MISMATCH_CHECK 2018-03-02 00:13:45 -05:00
m-nocp.decode target/arm: Implement new v8.1M VLLDM and VLSTM encodings 2021-03-03 19:01:33 -05:00
m_helper.c target/arm/m_helper: Silence GCC 10 maybe-uninitialized error 2021-03-04 15:16:55 -05:00
Makefile.objs target/arm: Do M-profile NOCP checks early and via decodetree 2021-02-26 11:17:23 -05:00
mte_helper.c qemu/atomic.h: rename atomic_ to qatomic_ 2021-03-08 14:34:35 -05:00
neon-dp.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
neon-ls.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
neon-shared.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
neon_helper.c target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree 2020-05-15 23:26:51 -04:00
op_addsub.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
op_helper.c target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate 2021-03-04 18:24:57 -05:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-03-04 13:38:22 -05:00
psci.c fix WFI/WFE length in syndrome register 2018-03-05 11:21:51 -05:00
sve.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
sve_helper.c target/arm: Update REV, PUNPK for pred_desc 2021-03-04 15:15:47 -05:00
syndrome.h target/arm: Split out syndrome.h from internals.h 2021-03-04 18:44:07 -05:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
t32.decode target/arm: Implement M-profile "minimal RAS implementation" 2021-03-03 19:07:27 -05:00
tlb_helper.c target/arm: set HPFAR_EL2.NS on secure stage 2 faults 2021-03-04 14:54:33 -05:00
translate-a64.c target/arm: Speed up aarch64 TBL/TBX 2021-03-08 11:31:24 -05:00
translate-a64.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
translate-neon.inc.c arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
translate-sve.c target/arm: Update REV, PUNPK for pred_desc 2021-03-04 15:15:47 -05:00
translate-vfp.inc.c target/arm: Implement FPCXT_NS fp system register 2021-03-03 20:02:36 -05:00
translate.c target/arm: Implement SCR_EL2.EEL2 2021-03-04 15:03:08 -05:00
translate.h target/arm: Rearrange {sve,fp}_check_access assert 2021-02-26 13:56:27 -05:00
unicorn.h Move target-* CPU file into a target/ folder 2018-03-01 22:50:58 -05:00
unicorn_aarch64.c unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
unicorn_arm.c arm/translate: Do not tracecode when in an IT block 2021-02-07 19:14:32 +00:00
vec_helper.c target/arm: Speed up aarch64 TBL/TBX 2021-03-08 11:31:24 -05:00
vec_internal.h arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2021-03-02 13:30:35 -05:00
vfp.decode target/arm: Implement VLDR/VSTR system register 2021-03-03 18:42:05 -05:00
vfp_helper.c target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension 2021-03-01 20:36:02 -05:00